LTC3731 Linear Technology, LTC3731 Datasheet - Page 20

• Manufacturer Part Number: LTC3731
• Description: Synchronous Buck Switching Regulator Controller
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
LTC3731
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point, the phase comparator output is
open and the filter capacitor C
PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin. When using
multiple ICs for a phase-locked system, the PLLFLTR pin
of the master oscillator should be biased at a voltage that
will guarantee the slave oscillator(s) ability to lock onto the
master’s frequency. A voltage of 1.7V or below applied to
the master oscillator’s PLLFLTR pin is recommended in
order to meet this requirement. The resultant operating
frequency will be approximately 550kHz for 1.7V.
The loop filter components (C
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
acquires lock. Typically R
0.01µF to 0.1µF.
Minimum On-Time Considerations
Minimum on-time, t
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
20
t
ON MIN
PLLIN
EXTERNAL
(
OSC
Figure 9. Phase-Locked Loop Block Diagram
)
<
V f
PHASE
DETECTOR/
OSCILLATOR
V
LP
50k
IN
OUT
( )
and R
U
ON(MIN)
FREQUENCY
DETECTOR
DIGITAL
PHASE/
OSC
LP
U
LP
, is the smallest time duration
determine how fast the loop
=10k and C
LP
LP
holds the voltage. The IC
, R
2.4V
W
LP
) smooth out the
3731 F09
LP
PLLFLTR
R
10k
ranges from
LP
U
C
LP
If the duty cycle falls below what can be accommodated by
the minimum on-time, the IC will begin to skip every other
cycle, resulting in half-frequency operation. The output
voltage will continue to be regulated, but the ripple current
and ripple voltage will increase.
The minimum on-time for the IC is generally about 110ns.
However, as the peak sense voltage decreases the mini-
mum on-time gradually increases. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that is low enough
in value to provide sufficient ripple amplitude to meet the
minimum on-time requirement. As a general rule, keep
the inductor ripple current for each channel equal to or
greater than 30% of I
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
where L1, L2, etc. are the individual losses as a percentage
of input power.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
%Efficiency = 100% – (L1 + L2 + L3 + ...)
OUT
OUT
to its steady-state value. During this recovery
, generating the feedback error signal that
LOAD
OUT
OUT(MAX)
• ESR, where ESR is the effective
. ∆I
LOAD
at V
also begins to charge or
IN(MAX)
OUT
.
shifts by an
3731fa