LTC4006 Linear Technology, LTC4006 Datasheet - Page 15

• Manufacturer Part Number: LTC4006
• Description: Standalone Li-Ion Battery Charger
• Manufacturer: Linear Technology

PACKAGE
APPLICATIO S I FOR ATIO
5. Place output capacitors next to the sense resistor
6. Output capacitor ground connections need to feed
General Rules
7. Connection of switching ground to system ground or
8. Route analog ground as a trace tied back to IC ground
(0.178 – 0.249)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
.007 – .0098
current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time with
smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at the
sense resistor location.
output and ground.
into same copper that connects to the input capacitor
ground before tying back into system ground.
internal ground plane should be single point. If the
system has an internal system ground plane, a good
way to do this is to cluster vias into a single star point
to make the connection.
(analog ground pin if present) before connecting to
V
IN
(0.38 0.10)
.015 .004
Figure 12. High Speed Switching Path
(0.406 – 1.270)
C2
.016 – .050
(MILLIMETERS)
INCHES
DESCRIPTION
45
CIRCULATING
FREQUENCY
U
SWITCH NODE
PATH
HIGH
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
0 – 8 TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
U
(0.203 – 0.305)
.008 – .012
(1.351 – 1.727)
.053 – .068
L1
W
D1
U
16-Lead Plastic SSOP (Narrow .150 Inch)
C3
(Reference LTC DWG # 05-08-1641)
U
4006 F12
BAT
(0.635)
.0250
BSC
V
BAT
(0.102 – 0.249)
.004 – .0098
GN Package
(5.817 – 6.198)
.229 – .244
9. A good rule of thumb for via count for a given high
10. If possible, place all the parts listed above on the same
11. Copper fills or pours are good for all power connec-
12. For best current programming accuracy provide a
It is important to keep the parasitic capacitance on the R
CSP and BAT pins to a minimum. The traces connecting
these pins to their respective resistors should be as short
as possible.
any other ground. Avoid using the system ground
plane. CAD trick: make analog ground a separate
ground net and use a 0 resistor to tie analog ground
to system ground.
current path is to use 0.5A per via. Be consistent.
PCB layer.
tions except as noted above in Rule 3. You can also use
copper planes on multiple layers in parallel too—this
helps with thermal management and lower trace in-
ductance improving EMI performance further.
Kelvin connection from R
Figure 12 as an example.
16 15 14 13
1
2 3
Figure 13. Kelvin Sensing of Charging Current
(4.801 – 4.978)
.189 – .196*
4
12 11 10 9
5 6 7
DIRECTION OF CHARGING CURRENT
8
GN16 (SSOP) 0502
(3.810 – 3.988)
.150 – .157**
CSP
(0.229)
.009
REF
R
SNS
SENSE
.254 MIN
.0165 .0015
BAT
RECOMMENDED SOLDER PAD LAYOUT
to CSP and BAT. See
4006 F13
LTC4006
.045 .005
.150 – .165
sn4006 4006is
15
.0250 TYP
T
,