TUA6012XS Siemens Semiconductor Group, TUA6012XS Datasheet - Page 12

• Manufacturer Part Number: TUA6012XS
• Description: Components for Entertainment Electronics
• Manufacturer: Siemens Semiconductor Group

Semiconductor Group
The software-switched ports P0, P1, P2 and P3 are general-purpose open-collector
outputs. The test bit T1 = 1, switches the test signals
and
The lock detector resets the lock flag FL when the width of the charge pump current
pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, when
FL = 1, the maximum deviation of the input frequency from the programmed frequency
is given by
where
frequency and
page 27). As the charge pump pulses at 62.5 kHz (=
for FL to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns
for eight consecutive
set after the loop regains lock.
2.3
Data is exchanged between the processor and the PLL via the
generated by the processor (input SCL), while pin SDA functions as an input or output
depending on the direction of the data (open collector, external pull-up resistor). Both
inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity
of the
The data from the processor pass through an
function the data are subsequently stored in registers. If the bus is free, both lines will be
in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition
and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains
HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information
transfer takes place during SCL = LOW, and the data is forwarded to the control logic on
the positive clock edge.
The table ”Bit Allocation” (see ”Bit Allocation Read/Write” on page 13) should be referred
to the following description. All telegrams are transmitted byte-by-byte, followed by a
ninth clock pulse, during which the control logic returns the SDA line to LOW
(acknowledge condition). The first byte is comprised of seven address bits. These are
used by the processor to select the PLL from several peripheral components (chip
select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read
from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the first or
third data byte determines whether a divider ratio or control information is to follow. In
C
y
I
I
2
I
(divided input signal) to P0 and P1 respectively. P0, P1 are bidirectional.
C Bus.
P
2
C-Bus Interface
is the charge pump current,
C
1
,
C
2
f
ref
the capacitances in the loop filter (see ”Application Circuits” on
periods. Therefore it takes between 128 and 144 s for FL to be
f
= ±
I
P
(
K
VCO
/
K
f
Q
12
VCO
) (
C
1
the VCO gain,
I
+
2
C-Bus controller. Depending on their
C
2
f
) / (
ref
f
ref
(4 MHz / reference divider ratio)
C
), it takes a maximum of 16 s
1
C
2
)
f
Q
I
2
the crystal oscillator
C Bus. The clock is
TUA 6012
TUA 6014
1998-09-01