LV25400W Sanyo Semicon Device, LV25400W Datasheet - Page 34

• Manufacturer Part Number: LV25400W
• Description: DSP Tuner Front End
• Manufacturer: Sanyo Semicon Device

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Continued from preceding page.
(11)
(12)
(13)
(14)
(15)
(16)
No.
2.7V REG
ADJ
REG_ADJ0
REG_ADJ1
Crystal oscillator selection
XS0, XS1
HD (wide) IF AGC amplifier
variation correction bits
ADJ_W0
ADJ_W1
ADJ_W2
ADJ_W3
DO pin control data (2)
IL0, IL1
DO pin control data (1)
ULD
DT0, DT1
Unlock state detection data
UL0, UL1
Control block/data
• Adjusts the 2.7 V regulator
• Selects the crystal element.
• Corrects for sample-to-sample variations in the IF AGC amplifier gain
• Controls the DO pin output
• Determines the DO pin output.
The following item (5) must also be set when monitoring the unlock detection signal.
• Selects the phase error (øE) detection width used to judge the PLL locked state.
2.7V REG ADJ
DO pin control data (2)
Since there are no connected pins in the current product, the open setting must be
used.
DO pin control data (1)
If a phase error in excess of the øE detection width from the table below occurs, the
PLL is seen as being in the unlocked state.
When the PLL is seen as being unlocked, the detection pin (DO) is set low.
XS1
ULD
UL1
0 0
0 1
1 0
1 1
IL1
DO
φE
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
Amount of correction : ±5 dB
4 bit
-23mV
(Center value)
+23mV
+64mV
XS0
UL0
IL0
IL0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
LV25400W
Open
The I3 pin state (unused)
The I2 pin state (unused)
The I1 pin state (unused)
Stopped
0
±0.5µs
±1µs
φE detection width
DT0
0
1
0
1
0
1
0
1
Illegal value
Illegal value
Illegal value
X’tal OSC
4.5MHz
Unlock state output
1 to 2ms
Description
IN
Low when not locked.
(See DO control (2))
(See DO control (2))
Monitor 1 (unused)
Monitor 2 (unused)
Monitor 1 (unused)
Monitor 2 (unused)
Delay
Open
φE is output directly
φE is delayed by 1 to 2 ms.
φE is delayed by 1 to 2 ms.
Detection pin output
DO pin
Open
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UL0, UL1
ULD
DT0, DT1
Related data
No.A0633-34/42
Datasheet pdf - http://www.DataSheet4U.net/