MBM29F200TC Fujitsu Media Devices Limited, MBM29F200TC Datasheet - Page 15

• Manufacturer Part Number: MBM29F200TC
• Description: 2M (256K X 8/128K X 16) BIT
• Manufacturer: Fujitsu Media Devices Limited

www.datasheet4u.com
Autoselect Command
Byte/Word Programming
Chip Erase
The device will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A
voltage onto the address lines is not generally desired system design practice.
The device contains an autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address XX01H for 16 (XX02H for 8) returns the device code (MBM29F200TC = 51H and
MBM29F200BC = 57H for 8 mode; MBM29F200TC = 2251H and MBM29F200BC = 2257H for 16 mode).
(See Tables 4.1 and 4.2.)
All manufacturer and device codes will exhibit odd parity with DQ
Scanning the sector addresses ( A
at device output DQ
the protected sector (See Tables 2 and 3).
To terminate the operation, it is necessary to write the read/reset command sequence into the register and also
to write the autoselect command during the operation, execute it after writing read/reset command sequence.
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the
rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins
programming. Upon executing the Embedded Program
required to provide further controls or timings. The device will automatically provide adequate internally generated
program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ
bit at which time the devices return to the read mode and addresses are no longer latched (see Table 8, Hardware
Sequence Flags) Therefore, the devices require that a valid address to the devices be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
Figure 19 illustrates the Embedded Programming Algorithm using typical command strings and bus operations.
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
MBM29F200TC
0
for a protected sector. The programming verification should be perform margin mode on
16
, A
15
, A
14
, A
13
-55/-70/-90
, and A
TM
12
) while (A
Algorithm command sequence the system is not
/MBM29F200BC
9
to a high voltage. However, multiplexing high
7
defined as the parity bit.
6
, A
1
, A
0
7
) = (0, 1, 0) will produce a logical “1”
is equivalent to data written to this
-55/-70/-90
15