MX25L1635D Macronix International, MX25L1635D Datasheet
MX25L1635D
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MX25L1635D Summary of contents
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... P/N: PM1374 MX25L1635D DATASHEET 1 MX25L1635D REV. 1.5, OCT. 01, 2008 ...
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... I/O Read Mode (2READ) ....................................................................................................................... 18 ( I/O Read Mode (4READ) ....................................................................................................................... 19 (10) Sector Erase (SE) ..................................................................................................................................... 19 (11) Block Erase (BE) ...................................................................................................................................... 19 (12) Chip Erase (CE) ........................................................................................................................................ 20 (13) Page Program (PP) ................................................................................................................................... 20 (14 I/O Page Program (4PP) ...................................................................................................................... 21 (15) Continuously program mode (CP mode) ..................................................................................................... 21 (16) Deep Power-down (DP) ............................................................................................................................. 21 P/N: PM1374 MX25L1635D Contents 2 REV. 1.5, OCT. 01, 2008 ...
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... Figure 20 I/O Page Program (4PP) Sequence (Command 38) ................................................................... 36 Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) ....................... 37 Figure 22. Sector Erase (SE) Sequence (Command 20) .................................................................................. 37 Figure 23. Block Erase (BE) Sequence (Command D8) ................................................................................... 37 Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) ............................................................................ 38 Figure 25. Deep Power-down (DP) Sequence (Command B9) .......................................................................... 38 P/N: PM1374 MX25L1635D 3 REV. 1.5, OCT. 01, 2008 ...
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... Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command DF) ............. 39 Figure 29. Power-up Timing .............................................................................................................................. 40 Table 11. Power-Up Timing and VWI Threshold ................................................................................................. 40 INITIAL DELIVERY STATE ....................................................................................................................................... 40 RECOMMENDED OPERATING CONDITIONS .......................................................................................................... 41 ERASE AND PROGRAMMING PERFORMANCE ...................................................................................................... 42 LATCH-UP CHARACTERISTICS ............................................................................................................................... 42 ORDERING INFORMATION ...................................................................................................................................... 43 PART NAME DESCRIPTION ..................................................................................................................................... 44 PACKAGE INFORMATION ......................................................................................................................................... 45 REVISION HISTORY ................................................................................................................................................. 49 www.DataSheet4U.com P/N: PM1374 MX25L1635D 4 REV. 1.5, OCT. 01, 2008 ...
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... Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) P/N: PM1374 MX25L1635D 16M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH 5 REV. 1.5, OCT. 01, 2008 ...
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... Hardware write protection or serial data Input/Output for 4 x I/O read mode • NC/SIO3 - NC pin or serial data Input/Output for 4 x I/O read mode • PACKAGE - 16-pin SOP (300mil) - 8-land WSON (6x5mm) - 8-pin SOP (200mil, 150mil) - All Pb-free devices are RoHS Compliant www.DataSheet4U.com P/N: PM1374 MX25L1635D 6 REV. 1.5, OCT. 01, 2008 ...
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... The MX25L1635D are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When two or four I/O read mode, the structure becomes 8,388,608 bits 4,194,304 bits x 4. The MX25L1635D feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO) ...
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... GND WP#/SIO2 PIN DESCRIPTION SYMBOL CS# SI/SIO0 SO/SIO1 SCLK WP#/SIO2 Write protection: connect to GND or Serial V NC/SIO3 V V VCC V GND 8 MX25L1635D CS# 1 VCC 8 2 SO/SIO1 NC/SIO3 7 3 WP#/SIO2 6 SCLK GND 4 SI/SIO0 5 DESCRIPTION Chip Select Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/O read ...
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... BLOCK DIAGRAM SI/SIO0 CS# WP#/SIO2 NC/SIO3 SCLK SO/SIO1 www.DataSheet4U.com P/N: PM1374 Address Generator Memory Array Page Buffer Data Register SRAM Buffer Mode State Logic Machine Generator Clock Generator 9 MX25L1635D Y-Decoder Sense Amplifier HV Output Buffer REV. 1.5, OCT. 01, 2008 ...
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... DATA PROTECTION The MX25L1635D is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences ...
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... Size Standard Factory Lock 128-bit ESN (electrical serial number) 384-bit N/A 11 MX25L1635D Customer Lock Determined by customer REV. 1.5, OCT. 01, 2008 ...
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... MX25L1635D Address Range Sector 255 0FF000h 0FFFFFh . . . . . . . . . 240 0F0000h 0F0FFFh 239 0EF000h 0EFFFFh . . . . . . . . . 224 0E0000h 0E0FFFh 223 0DF000h 0DFFFFh . . . . . . . . . 208 0D0000h 0D0FFFh 207 0CF000h 0CFFFFh ...
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... CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1374 shift in MSB 13 MX25L1635D shift out MSB REV. 1.5, OCT. 01, 2008 ...
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... ID & device secured secured ID OTP OTP m ode m ode 14 MX25L1635D (read 2RE 4RE data (fas t x I/O read x I/O read read data and and) Note1 03 (hex ) 0B (hex ) B B (hex ) ...
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... RDID operation can use CS# to high at any time during data out. (see Figure 11.) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1374 MX25L1635D 15 REV. 1.5, OCT. 01, 2008 ...
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... BP3 BP2 BP1 (level of (level of (level of protected block) protected block) (note1) (note1) (note1) Non- volatile bit Non- volatile bit Non- volatile bit 16 MX25L1635D bit2 bit1 bit0 BP0 WEL WIP (level of (write enable (write in protected block) latch) progress bit) 1= write 1= write enable ...
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... If SRWD bit=1 but WP#/SIO2 is low impossible to write the Status Register even if the WEL bit has previously been set rejected to write the Status Register and not be executed. P/N: PM1374 MX25L1635D WP# and SRWD bit status WP#=1 and SRWD bit=0, or The protected area cannot WP#=0 and SRWD bit= program or erase ...
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... CS# to high at any time during data out (see Figure 16 for 2 x I/O Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1374 MX25L1635D 18 REV. 1.5, OCT. 01, 2008 ...
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... The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K- byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before P/N: PM1374 MX25L1635D 19 REV. 1.5, OCT. 01, 2008 ...
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... Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. P/N: PM1374 MX25L1635D 20 REV. 1.5, OCT. 01, 2008 ...
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... CP mode. (16) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the P/N: PM1374 MX25L1635D 21 REV. 1.5, OCT. 01, 2008 ...
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... Table Definitions in next page. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. P/N: PM1374 MX25L1635D 22 REV. 1.5, OCT. 01, 2008 ...
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... Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode. P/N: PM1374 MX25L1635D Memory type Memory Density C2 24 Electronic ID 24 Device MX25L1635D 15 REV. 1.5, OCT. 01, 2008 ...
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... Continuously x Program mode x (CP mode) 0=normal Program mode reserved reserved 1=CP mode (default=0) volatile bit volatile bit volatile bit 24 MX25L1635D bit2 bit1 bit0 LDSO (indicate if Secrured OTP x lock-down indicator bit 0 = not lock- down 1 = lock-down 0 = non- reserved (cannot factory lock program/erase ...
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... At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress. www.DataSheet4U.com P/N: PM1374 MX25L1635D 25 REV. 1.5, OCT. 01, 2008 ...
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... Output Capacitance P/N: PM1374 VALUE -40° 85° C for Industrial grade -55° 125° C -0.5V to 4.6V -0.5V to 4.6V -0.5V to 4.6V Figure 3. Maximum Positive Overshoot Waveform 20ns Vcc + 2.0V 20ns MIN. TYP 26 MX25L1635D 20ns Vcc 20ns 20ns MAX. UNIT CONDITIONS 6 pF VIN = VOUT = 0V REV. 1.5, OCT. 01, 2008 ...
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... AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns CL 6.2K ohm CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for 86MHz & 104MHz, 75MHz@2xI/O and 75MHz@4xI/O) 27 MX25L1635D Output timing referance level 0.5VCC 2.7K ohm +3.3V DIODES=IN3064 OR EQUIVALENT REV. 1.5, OCT. 01, 2008 ...
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... VCC+0.4 0.4 VCC-0.2 28 MX25L1635D TEST CONDITIONS uA VCC = VCC Max VIN = VCC or GND uA VCC = VCC Max VIN = VCC or GND uA VIN = VCC or GND CS# = VCC uA VIN = VCC or GND CS# = VCC mA f=86MHz and 104MHz fQ=75MHz (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open ...
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... Value guaranteed by characterization, not 100% tested in production. 3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 4, 5. P/N: PM1374 MX25L1635D Min. Typ. D.C. D.C. 4.8 4 ...
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... Timing Analysis Figure 6. Serial Input Timing CS# tCHSL SCLK tDVCH SI SO Figure 7. Output Timing CS# SCLK www.DataSheet4U.com tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1374 tSLCH tCHSH tCHDX tCLCH MSB High-Z tCH tCLQV 30 MX25L1635D tSHSL tSHCH tCHCL LSB tCL tSHQZ LSB tQLQH tQHQL REV. 1.5, OCT. 01, 2008 ...
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... Figure 9. Write Enable (WREN) Sequence (Command 06) www.DataSheet4U.com Figure 10. Write Disable (WRDI) Sequence (Command 04) P/N: PM1374 High-Z CS SCLK Command SI 06 High SCLK Command SI 04 High MX25L1635D tSHWL REV. 1.5, OCT. 01, 2008 ...
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... Status Register Out MSB command MSB High-Z 32 MX25L1635D Device Identification MSB Status Register Out MSB Status Register In ...
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... High Configurable Dummy Cycle DATA OUT MSB 33 MX25L1635D Data Out 1 Data Out MSB 0 47 DATA OUT ...
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... EB(hex) bit20, bit16..bit0 address bit21, bit17..bit1 address bit22, bit18..bit2 address bit23, bit19..bit3 34 MX25L1635D dummy Data Output cycle data dummy bit6, bit4, bit2...bit0, bit6, bit4.... data dummy bit7, bit5, bit3...bit1, bit7, bit5.... ...
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... P4 P0 bit4, bit0, bit4.... P5 P1 bit5 bit1, bit5.... P6 P2 bit6 bit2, bit6.... P7 P3 bit7 bit3, bit7.... 35 MX25L1635D dummy Data Output cycles data bit4, bit0, bit4.... data bit5 bit1, bit5.... data bit6 bit2, bit6.... data bit7 bit3, bit7 ...
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... Command 6 Address cycle MX25L1635D Data Byte MSB Data Byte 256 ...
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... Byte 0, Byte1 status ( Command 24 Bit Address MSB Command 24 Bit Address MSB 37 MX25L1635D data in 04 (hex) 05 (hex REV. 1.5, OCT. 01, 2008 ...
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... Command Dummy Bytes MSB Electronic Signature Out 7 MSB Deep Power-down Mode 38 MX25L1635D Stand-by Mode Deep Power-down Mode RES2 Stand-by Mode REV. 1.5, OCT. 01, 2008 ...
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... Dummy Bytes High ADD ( Manufacturer MSB 39 MX25L1635D Stand-by Mode 47 Device MSB MSB REV. 1.5, OCT. 01, 2008 ...
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... The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1374 Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed tVSL tPUW 40 MX25L1635D Read Command is Device is fully allowed accessible time Min. Max. ...
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... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1374 tCHSL tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 41 MX25L1635D tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 20 500000 us/V ...
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... LATCH-UP CHARACTERISTICS Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. www.DataSheet4U.com P/N: PM1374 MX25L1635D Min. TYP. (1) Max. (2) 40 100 60 300 ...
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... ORDERING INFORMATION PART NO. CLOCK (MHz) MX25L1635DMI-12G 86 MX25L1635DM1I-12G 86 MX25L1635DM2I-12G 86 MX25L1635DZNI-12G 86 MX25L1635DM2I-10G 104 www.DataSheet4U.com P/N: PM1374 OPERATING STANDBY Temperature PACKAGE Remark CURRENT MAX. CURRENT MAX. (mA) (uA -40° C~85° C 16-SOP 25 20 -40°C~85° -40°C~85° -40°C~85° -40°C~85°C 43 MX25L1635D Pb-free ...
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... MX 25 www.DataSheet4U.com P/N: PM1374 L 1635D OPTION: G: Pb-free SPEED: 12: 86MHz 10: 104MHz TEMPERATURE RANGE: I: Industrial (-40˚ 85˚ C) PACKAGE: ZN: WSON M: 300mil 16-SOP M1: 150mil 8-SOP M2: 200mil 8-SOP DENSITY & MODE: 1635D: 16Mb standard type TYPE DEVICE: 25: Serial Flash 44 MX25L1635D REV. 1.5, OCT. 01, 2008 ...
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... PACKAGE INFORMATION www.DataSheet4U.com P/N: PM1374 MX25L1635D 45 REV. 1.5, OCT. 01, 2008 ...
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... P/N: PM1374 MX25L1635D 46 REV. 1.5, OCT. 01, 2008 ...
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... P/N: PM1374 MX25L1635D 47 REV. 1.5, OCT. 01, 2008 ...
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... P/N: PM1374 MX25L1635D 48 REV. 1.5, OCT. 01, 2008 ...
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... Rewrite 4xI/O Read performance enhance mode process flow description 4. Modified figure 2 & 3 waveform 1.5 1. Revised sector erase time spec from 90ms(typ.) to 60ms(typ.) 2. Revised sector erase time spec from 120ms(max.) to 300ms(max.) P29 3. Revised block erase time spec from 1s(typ.) to 0.7s(typ.) www.DataSheet4U.com P/N: PM1374 MX25L1635D Page P1 P10,18,19 P16 P13,19,20 P29 P19,35 P5,27,28,29, ...
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... Macronix Europe N.V. Koningin Astridlaan 59, Bus 1 1780 Wemmel Belgium Tel: +32-2-456-8020 Fax: +32-2-456-8021 Singapore Office Macronix Pte. Ltd. 1 Marine Parade Central #11-03 Parkway Centre Singapore 449408 Tel: +65-6346-5505 Fax: +65-6348-8096 MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 50 MX25L1635D ...