MX26L1620 Macronix International, MX26L1620 Datasheet - Page 12

• Manufacturer Part Number: MX26L1620
• Description: 16M-BIT [1M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM
• Manufacturer: Macronix International

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Table 6. Write Operation Status
WRITE OPERSTION STATUS
The device provides several bits to determine the sta-
tus of a write operation: Q5, Q6, Q7. The following sub-
sections describe the functions of these bits. Q7, and
Notes: 1.Performing successive read operations from any address will cause Q6 to toggle.
SETUP AUTOMATIC CHIP ERASE
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.
The MX26L1620 contains a Silicon-ID-Read operation to
supplement traditional PROM programming methodology.
The operation is initiated by writing the read silicon ID
command sequence into the command register. Follow-
ing the command write, a read cycle with A6=VIL,
A1=VIL, A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A6=VIL, A1=VIL, A0=VIH returns the
device code of 22FEH for MX26L1620.
AUTOMATIC CHIP ERASE COMMAND
The device does not require the system to preprogram
prior to erase. The Automatic Erase algorithm automati-
cally preprograms and verifies the entire memory for an
P/N:PM0827
TABLE 5. SILICON ID CODE
In Progress Word Program in Auto Program Algorithm
Exceeded
Time Limits Auto Erase Algorithm
Pins
Manufacture code
Device code for MX26L1620 VIH VIL VIL
Status
Auto Erase Algorithm
Word Program in Auto Program Algorithm
A0
VIL
A1
VIL VIL
A6
Q15 Q7
Q8
00H
22H
|
1
1
12
Q6 each offer a method for determining whether a pro-
gram or erase operation is complete or in progress. These
three bits are discussed first.
all zero data pattern prior to electrical erase. The system
is not required to provide any controls or timings during
these operations. Table 4 shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Automatic
Erase algorithm are ignored. Note that a hardware reset
during the chip erase operation immediately terminates
the operation. The Chip Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase op-
eration by using Q7, Q6. See "Write Operation Status"
for information on these status bits. When the Automatic
Erase algorithm is complete, the device returns to read-
ing array data and addresses are no longer latched.
Figure 5 illustrates the algorithm for the erase opera-
tion.See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to Figure 4 for tim-
ing diagrams.
Q6
1
1
Q5
0
1
Q4
0
1
Q7
Q7
Q7
0
0
MX26L1620
Q3 Q2 Q1 Q0 Code(Hex)
0
1
0
1
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Note1
Q6
1
1
REV. 0.4, JAN. 31, 2002
0
0
Q5
00C2H
22FEH
0
0
1
1