MX29F022 Macronix, MX29F022 Datasheet
MX29F022
Related parts for MX29F022
MX29F022 Summary of contents
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... MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F022T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility ...
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... MX29F022T Sector Architecture ...
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... Block Diagram CONTROL CE INPUT OE LOGIC WE RESET ADDRESS LATCH A0-A17 AND BUFFER Q0-Q7 P/N:PM0556 MX29F022/022N PROGRAM/ERASE HIGH VOLTAGE MX29F022T/B FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 3 WRITE STATE MACHINE (WSM) STATE REGISTER COMMAND DATA DECODER COMMAND DATA LATCH REV ...
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... Automatic Programming algorithm. The Automatic Programming algorithm does not require the system to time out or verify the data programmed. The typical chip programming time of the MX29F022T/B at room tem- perature is less than 2 seconds. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 10ms erase pulses according to MXIC's High Reliability Chip Erase algorithm ...
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... Address (SA). Write Sequence may be initiated with A11~A17 in either state. 4. For Chip Protect Verify operation:If read out data is 01H, it means the chip has been protected. If read out data is 00H, it means the chip is still not being protected. P/N:PM0556 MX29F022/022N Second Bus Third Bus Fourth Bus Cycle ...
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... TABLE 2. MX29F022T/B BUS OPERATION Pins Mode Read Silicon ID Manfacturer Code(1) Read Silicon ID Device Code(1) Read Standby Output Disable Write Chip Protect with 12V system(6) Chip Unprotect with 12V system(6) Verify chip Protect Code(5) with 12V system Chip Protect without 12V system (6) ...
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... ID command sequence into the command regis- ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 36H for MX29F022T,37H for MX29F022B. TABLE 3. EXPANDED SILICON ID CODE Pins A0 ...
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... The sector address is latched on the falling edge of WE, while the command(data) is latched on the rising edge P/N:PM0556 MX29F022/022N of WE. Sector addresses selected are loaded into internal register on the sixth falling edge of WE. Each successive sector load cycle started by the falling edge of WE must begin within 30us from the rising edge of the preceding WE ...
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... Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2.Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information. P/N:PM0556 MX29F022/022N Q7 Note1 Q7 0 ...
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... The Data Polling feature is active during Automatic Pro- gram/Erase algorithm or sector erase time-out.(see sec- tion Q3 Sector Erase Timer) Q6:Toggle BIT I The MX29F022T/B features a "Toggle Bit" method to indicate to the host system that the Auto Program/ Erase algorithms are either in progress or complete. During an Automatic Program or Erase algorithm op- eration, successive read cycles to any address cause Q6 to toggle ...
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... The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and P/N:PM0556 MX29F022/022N Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks ...
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... Performing a read operation with A1=VIH, it will produce a logical "1" for the protected status. CHIP UNPROTECT WITH 12V SYSTEM The MX29F022T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. ...
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... The details are shown in chip unprotect algorithm and waveform. POWER-UP SEQUENCE The MX29F022T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of a two-step command sequence. Vpp and Vcc power up sequence is not required ...
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... Temporary Sector Unprotect Operation (only for 29F022T/B) Temporary Sector Unprotect Completed(Note 2) Note : P/N:PM0556 MX29F022/022N Start RESET = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET = VIH 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V 2. All previously protected sectors are protected again. 14 REV. 1.1, JUN. 14, 2001 ...
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... RESET Setup Time for Temporary Sector Unprotect Note: Not 100% tested Temporary Sector Unprotect Timing Diagram (only for 29F022T/B) 12V RESET tVIDR CE WE tRSP P/N:PM0556 MX29F022/022N Test Setup Min Min Program or Erase Command Sequence 15 AllSpeed Options Unit 500 tVIDR REV ...
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... RESET High Time Before Read(See Note) Note: Not 100% tested (only for 29F002T/B) RESET TIMING WAVFORM CE, OE RESET Reset Timing NOT during Automatic Algorithms RESET Reset Timing during Automatic Algorithms P/N:PM0556 MX29F022/022N Test Setup MAX MIN MIN tRH tRP2 tReady tRP1 16 All Speed Options Unit ...
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... VIL min. = -2.0V for pulse width is equal to or less than 20 ns. 2.VIH max. = VCC + 1.5V for pulse width is equal to or less than VIH is over the specified maximum value, read operation cannot be guaranteed. P/N:PM0556 MX29F022/022N MIN. TYP MAX. 8 ...
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... Reference levels for measuring timing : 0.8V/2.0V or 70ns max. NOTE: 1.tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. P/N:PM0556 MX29F022/022N VCC = 5V ± ± ± ± ± 10%(VCC = 5V ± ± ± ± ± 5% for 29F022T/B-55) ...
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... READ TIMING WAVEFORMS VIH A0~17 VIL VIH CE VIL VIH WE VIL VIH OE VIL HIGH Z VOH DATA Q0~7 VOL P/N:PM0556 MX29F022/022N ADD Valid tCE tDF tOE tACC tOH DATA Valid 19 HIGH Z REV. 1.1, JUN. 14, 2001 ...
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... ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2. 4. All current are in RMS unless otherwise noted. P/N:PM0556 MX29F022/022N VCC = 5V ± ± ± ± ± 10%(VCC = 5V ± ± ± ± ± 5% for 29F022/022N-55) MIN ...
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... NOTES: 1.tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2.Under condition of VCC=5V±5%,CL=50pF, VIH/VIL=3.0V/0V, VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA. P/N:PM0556 MX29F022/022N VCC = 5V ± ± ± ± ± 10%(VCC=5V± ± ± ± ± 5% for 29F022T/B-55) 29F022T/B-55(Note2) 29F022T/B-70 29F022T/B-90 MIN ...
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... TEST CL=100pF Including jig capacitance for 29F022/022N-70, 29F022/022N-90,29F022/022N-12 CL=50pF Including jig capacitance for 29F022/022N-55 SWITCHING TEST WAVEFORMS(I) for MX29F022/022N-70/90/120 2.4V 0.45V AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are <20ns. ...
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... COMMAND WRITE TIMING WAVEFORM VCC 5V VIH ADD A0~17 VIL tAS VIH WE VIL tOES CE VIH VIL OE VIH VIL VIH DATA Q0-7 VIL P/N:PM0556 MX29F022/022N ADD Valid tAH tCEP tCWC tCS tCH tDS tDH DIN 23 tCEPH1 REV. 1.1, JUN. 14, 2001 ...
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... Command #AAH (Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2:Toggle bit P/N:PM0556 MX29F022/022N polling and toggle bit checking after automatic verification starts. Device outputs DATA during programming and DATA after programming on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing ...
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... AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address NO Invalid Command Auto Program Completed P/N:PM0556 MX29F022/022N START NO Toggle Bit Checking Q6 not Toggled YES Verify Byte Ok YES Auto Program Exceed Timing Limit ...
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... TOGGLE BIT ALGORITHM NO Notes: 1.Read toggle bit Q6 twice to determine whether or not it is toggle. See text. 2.Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See text. P/N:PM0556 MX29F022/022N START Read Q7~Q0 (Note 1) Read Q7~Q0 NO Toggle Bit Q6 =Toggle? YES Q5=1? YES (Note 1,2) Read Q7~Q0 Twice ...
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... Command #AAH Command #55H (Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit P/N:PM0556 MX29F022/022N automatic erase starts. Device outputs "0" during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) 555H 555H 2AAH ...
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... Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Toggle Bit Checking Q6 not Toggled NO Invalid DATA Polling Command Auto Chip Erase Completed P/N:PM0556 MX29F022/022N NO YES YES YES Reset . Auto Chip Erase Exceed Timing-Limit ...
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... Command #AAH Command #55H (Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit P/N:PM0556 MX29F022/022N checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) Sector Address0 555H ...
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... Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Toggle Bit Checking Load Other Sector Addrss If Necessary (Load Other Sector Address) Toggle Bit Checking Auto Sector Erase Completed P/N:PM0556 MX29F022/022N START NO Invalid Command Q6 Toggled ? YES NO Last Sector to Erase ...
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... ERASE SUSPEND/ERASE RESUME FLOWCHART P/N:PM0556 MX29F022/022N START Write Data B0H NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H Continue Erase Another NO Erase Suspend ? YES 31 REV. 1.1, JUN. 14, 2001 ...
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... A9 tVLHT 12V 5V OE tVLHT WE CE Data TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V A1 12V 5V A9 tVLHT A6 12V 5V OE tVLHT WE CE Data P/N:PM0556 MX29F022/022N tWPP 1 tOESP tWPP 2 tOESP 32 Verify tVLHT 01H tOE Verify tVLHT 00H tOE REV. 1.1, JUN. 14, 2001 ...
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... CHIP PROTECTION ALGORITHM FOR SYSTEM WITH 12V Device Failed P/N:PM0556 MX29F022/022N START PLSCNT=1 OE=VID,A9=VID,CE=VIL A6=VIL Activate WE Pulse Time Out 10us Set WE=VIH, CE=OE=VIL A9 should remain VID Read from Sector No Addr=SA, A1=1 No Data=01H? PLSCNT=32? Yes Remove VID from A9 Device Failed Write Reset Command ...
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... CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V Read Data from Device P/N:PM0556 MX29F022/022N START PLSCNT=1 Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse Time Out 12ms Increment Set OE=CE=VIL A9=VID,A1=1 No Data=00H? PLSCNT=1000? Yes Remove VID from A9 Device Failed Write Reset Command Chip Unprotect Complete ...
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... Note3: Protection verify:01H Un-protection verify:00H Note4: Must issue "unlock for chip protection/unprotection" command before chip protection/un-protection for a system without 12V provided. P/N:PM0556 MX29F022/022N A6,A9 & sector address are don't care during toggle bit polling period, or just be kept valid value in read window. X=Don't care ...
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... CHIP PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V Increment PLSCNT No PLSCENT=32? Yes Device Failed P/N:PM0556 MX29F022/022N START PLSCNT=1 Write "Unlock for chip protect/unprotect" Command OE=VID,A9=VID CE=VIL,A6=VIL Activate WE Pulse to start Data don't care No Toggle bit checking Q6 not Toggle Yes Set CE=OE=VIL ...
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... CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V Write "unlock for chip protect/unprotect" No P/N:PM0556 MX29F022/022N START PLSCNT=1 Command (Table 1) Set OE=A9=VIH CE=VIL,A6=1 Activate WE Pulse to start Data don't care Toggle bit checking Q6 not Toggled Yes Set OE=CE=VIL A9=VIH,A1=1 Read Data from Device No Data=00H? ...
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... ID CODE READ TIMING WAVEFORM MODE VCC 5V VID ADD VIH A9 VIL A1 VIH VIL ADD VIH A2-A8 A10-A17 VIL CE VIH VIL VIH WE VIL VIH OE VIL VIH DATA VIL Q0-Q7 P/N:PM0556 MX29F022/022N tACC tACC tCE tOE tOH DATA OUT C2H 38 tDF tOH DATA OUT 36H/37H REV. 1.1, JUN. 14, 2001 ...
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... MX29F022TTC-55 55 MX29F022TTC-70 70 MX29F022TTC-90 90 MX29F022TTC-12 120 MX29F022TQC-55 55 MX29F022TQC-70 70 MX29F022TQC-90 90 MX29F022TQC-12 120 MX29F022BPC-55 55 MX29F022BPC-70 70 MX29F022BPC-90 90 MX29F022BPC-12 120 MX29F022BTC-55 55 MX29F022BTC-70 70 MX29F022BTC-90 90 MX29F022BTC-12 120 MX29F022BQC-70 70 MX29F022BQC-90 90 MX29F022BQC-12 120 MX29F022NTPC-55 55 MX29F022NTPC-70 70 MX29F022NTPC-90 90 MX29F022NTPC-12 120 P/N:PM0556 MX29F022/022N OPERATING CURRENT STANDBY CURRENT MAX.(mA) MAX.(uA ...
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... ACCESS TIME (ns) MX29F022NTTC-55 55 MX29F022NTTC-70 70 MX29F022NTTC-90 90 MX29F022NTTC-12 120 MX29F022NTQC-55 55 MX29F022NTQC-70 70 MX29F022NTQC-90 90 MX29F022NTQC-12 120 MX29F022NBPC-55 55 MX29F022NBPC-70 70 MX29F022NBPC-90 90 MX29F022NBPC-12 120 MX29F022NBTC-55 55 MX29F022NBTC-70 70 MX29F022NBTC-90 90 MX29F022NBTC-12 120 MX29F022NBQC-70 70 MX29F022NBQC-90 90 MX29F022NBQC-12 120 P/N:PM0556 MX29F022/022N OPERATING CURRENT STANDBY CURRENT MAX.(mA) MAX.(uA ...
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... Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. DATA RETENTION PARAMETER Data Retention Time P/N:PM0556 MX29F022/022N LIMITS MIN. TYP.(2) MAX.( ...
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... PACKAGE INFORMATION 32-PIN PLASTIC DIP P/N:PM0556 MX29F022/022N 42 REV. 1.1, JUN. 14, 2001 ...
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... PLASTIC LEADED CHIP CARRIER (PLCC) P/N:PM0556 MX29F022/022N 43 REV. 1.1, JUN. 14, 2001 ...
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... PLASTIC TSOP P/N:PM0556 MX29F022/022N 44 REV. 1.1, JUN. 14, 2001 ...
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... Revision 0.9.4 to Revision 1.0: 2-1.Program/erase cycle times:10K cycles-->100K cycles 2-2.To add data retention 20 years 2-3.To remove A9 from the timing waveform of protection/ unprotection without 12V 2-4.Multi-sector erase time-out:30ms-->30us, 2-5.tBAL:80us-->100us 1.1 To modify "Package Information" P/N:PM0556 MX29F022/022N Page P1 P1,41 P1,41 P35 P8 P21 P42~44 45 Date ...
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... TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MX29F022/022N C L O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 46 ...