MX29LV008CB Macronix, MX29LV008CB Datasheet
MX29LV008CB
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MX29LV008CB Summary of contents
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FEATURES • Extended single - supply voltage range 2.7V to 3.6V • 1,048,576 x 8 • Single power supply operation - 3.0V only operation for read, erase and program operation • Fast access time: 55R/70/90ns • Fully compatible with MX29LV008BT/BB ...
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PIN CONFIGURATIONS 40 TSOP (Standard Type) (10mm x 20mm) A16 1 A15 2 A14 3 A13 4 A12 5 A11 WE# 9 RESET RY/BY# 12 A18 ...
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BLOCK STRUCTURE Table 1: MX29LV008CT SECTOR ARCHITECTURE Sector Sector Size SA0 64Kbytes SA1 64Kbytes SA2 64Kbytes SA3 64Kbytes SA4 64Kbytes SA5 64Kbytes SA6 64Kbytes SA7 64Kbytes SA8 64Kbytes SA9 64Kbytes SA10 64Kbytes SA11 64Kbytes SA12 64Kbytes SA13 64Kbytes SA14 64Kbytes ...
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... Table 2: MX29LV008CB SECTOR ARCHITECTURE Sector Sector Size SA0 16Kbytes SA1 8Kbytes SA2 8Kbytes SA3 32Kbytes SA4 64Kbytes SA5 64Kbytes SA6 64Kbytes SA7 64Kbytes SA8 64Kbytes SA9 64Kbytes SA10 64Kbytes SA11 64Kbytes SA12 64Kbytes SA13 64Kbytes SA14 64Kbytes SA15 64Kbytes SA16 64Kbytes ...
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BLOCK DIAGRAM CONTROL CE# OE# INPUT WE# LOGIC RESET# ADDRESS LATCH A0-A19 AND BUFFER Q0-Q7 P/N:PM1185 MX29LV008C T/B PROGRAM/ERASE HIGH VOLTAGE STATE FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV DATA LATCH PROGRAM DATA LATCH I/O ...
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AUTOMATIC PROGRAMMING The MX29LV008C T/B is byte programmable using the Automatic Programming algorithm. The Automatic Pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming ...
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Table 1 and Table 2). The rest of address bits, as shown in table3, are don't care. Once all neces- sary bits have been set as required, the ...
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TABLE 4. MX29LV008C T/B COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH F0H Read 1 RA Read Silicon Top Boot 4 555H AAH 2AAH ID Bottom Boot 4 555H AAH 2AAH Sector Protect 4 555H AAH ...
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COMMAND DEFINITIONS Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table ...
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REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array ...
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... Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 3EH for MX29LV008CT, 37H for MX29LV008CB. SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS Chip erase is a six-bus cycle operation. There are two " ...
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... Manufacture code VIL VIL Device code VIH VIL for MX29LV008CT Device code VIH VIL for MX29LV008CB Sector Protection X VIH Verification X VIH READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to re- trieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm ...
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SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the de- vice to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up command and Au- tomatic Sector Erase command. Upon executing the Automatic Sector Erase command, the ...
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Q7, Q6, or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a ...
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During an Automatic Program or Erase algorithm opera- tion, successive read cycles to any address cause Q6 to toggle. The system ...
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If this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still func- tional and may be used for the program or erase ...
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Q3 Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector ...
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CHIP UNPROTECT The MX29LV008C T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code recommended to protect all sectors before activating chip unprotect ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65 Ambient Temperature with Power Applied .... ...
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CAPACITANCE 1.0 MHz SYMBOL PARAMETER CIN1 Input Capacitance CIN2 Control Pin Capacitance COUT Output Capacitance Table 8. DC CHARACTERISTICS TA = -40 Symbol PARAMETER ILI Input Leakage Current ILIT A9 Input Leakage Current ...
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AC CHARACTERISTICS TA = -40 Table 9. READ OPERATIONS SYMBOL PARAMETER tRC Read Cycle Time (Note 1) tACC Address to Output Delay tCE CE# to Output Delay tOE OE# to Output Delay tDF OE# High to Output Float (Note1) tOEH ...
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SWITCHING TEST CIRCUITS DEVICE UNDER TEST SWITCHING TEST WAVEFORMS 3.0V 1.5V INPUT 0V AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. P/N:PM1185 ...
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Figure 1. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE# VIL VIH WE# VIL VIH OE# VIL HIGH Z VOH Outputs VOL VIH RESET# VIL P/N:PM1185 MX29LV008C T/B tRC ADD Valid tACC tCE tOE tOEH tACC tOH DATA Valid 23 ...
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AC CHARACTERISTICS TA = -40 Table 10. Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup Time tGHWL Read ...
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AC CHARACTERISTICS TA = -40 Table 11. Alternate CE# Controlled Erase/Program Operations SYMBOL PARAMETER tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup ...
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Figure 2. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE# VIL tOES CE# VIH VIL tCS OE# VIH VIL VIH Data VIL P/N:PM1185 MX29LV008C T/B ADD Valid tAH tWPH tWP tCWC tCH tDS tDH DIN 26 ...
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AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional verification by external control are not re- quired because these operations are executed automati- cally by internal control circuit. Programming comple- tion can be verified ...
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Figure 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM1185 MX29LV008C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? YES ...
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Figure 5. CE# CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase Address tWC tWH WE# tGHEL OE# tCP CE# tWS tDS Data tRH RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device. ...
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AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is verified automatically by internal control circuit. Erasure completion can be veri- fied by Data# Polling and toggle bit checking after ...
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Figure 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM1185 MX29LV008C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address ...
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AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector indicated by A12 to A18 are erased. External erase verify is not required because data are verified automatically by internal control circuit. Erasure comple- tion can be verified by Data# Polling and toggle bit ...
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Figure 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM1185 MX29LV008C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector ...
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Figure 10. ERASE SUSPEND/ERASE RESUME FLOWCHART Note: If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times, then the 10ms time delay must be put into consideration. P/N:PM1185 MX29LV008C T/B START ...
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Figure 11. SECTOR PROTECT/UNPROTECT TIMING WAVEFORM VID VIH RESET# SA, A6 A1, A0 Sector Protect or Sector Unprotect Data 60h 1us CE# WE# OE# Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0. P/N:PM1185 MX29LV008C T/B ...
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Figure 12. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID Increment PLSCNT No PLSCNT=25? Yes Device failed P/N:PM1185 MX29LV008C T/B START PLSCNT=1 RESET#=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H Yes Set up sector address Write 60H to sector ...
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Figure 13. IN-SYSTEM SECTOR UNPROTECTION ALGORITHM WITH RESET#=VID Increment PLSCNT No PLSCNT=1000? Yes Device failed P/N:PM1185 MX29LV008C T/B START PLSCNT=1 RESET#=VID Wait 1us No Temporary Sector First Write Unprotect Mode Cycle=60H ? Yes No All sector Protect all sectors protected? ...
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Figure 14. TIMING WAVEFORM FOR CHIP UNPROTECTION A1 12V 5V A9 tVLHT A6 12V 5V OE# tVLHT WE# CE# Data A18-A12 Notes: tVLHT (Voltage transition time)=4us min. tWPP1 (Write pulse width for sector protect)=100ns min. tWPP2 (Write pulse width for ...
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Figure 15. CHIP UNPROTECTION ALGORITHM Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1185 MX29LV008C T/B START Protect All Sectors PLSCNT=1 Set OE#=A9=VID CE#=VIL, A6=1 Activate WE# Pulse Time Out ...
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WRITE OPERATION STATUS Figure 16. DATA# POLLING ALGORITHM NOTE : 1.VA=Valid address for programming 2.Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1185 MX29LV008C T/B Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? No ...
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Figure 17. TOGGLE BIT ALGORITHM NO Program/Erase Operation Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM1185 MX29LV008C T/B Start Read Q7-Q0 ...
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Figure 18. Data# Polling Timings (During Automatic Algorithms) tRC Address VA tACC tCE CE# tCH tOE OE# tOEH WE# Q7 Q0-Q6 tBUSY RY/BY# NOTES: 1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, ...
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Figure 19. Toggle Bit Timings (During Automatic Algorithms) tRC VA Address tACC tCE CE# tCH tOE OE# tOEH WE# High Z Q6/Q2 tBUSY RY/BY# NOTES: 1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command ...
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Table 11. AC CHARACTERISTICS Parameter Std Description tREADY1 RESET# PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP RESET# Pulse Width (During Automatic ...
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Table 12. TEMPORARY SECTOR UNPROTECT Parameter Std. Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotect Note: Not 100% tested Figure 21. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM 12V RESET Vcc ...
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Figure 23. TEMPORARY SECTOR UNPROTECT ALGORITHM Temporary Sector Unprotect Completed(Note 2) Note : P/N:PM1185 MX29LV008C T/B Start RESET# = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET# = VIH 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V ...
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Figure 24. ID CODE READ TIMING WAVEFORM VCC 3V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A19 VIL CE# VIH VIL VIH WE# VIL VIH OE# VIL VIH DATA VIL Q0-Q7 ...
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RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) ...
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ERASE AND PROGRAMMING PERFORMANCE(1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Note: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured 3V. 3.Maximum values measured at ...
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... TIME (ns) MX29LV008CTTC-55R 55 MX29LV008CTTC-70 70 MX29LV008CTTC-90 90 MX29LV008CBTC-55R 55 MX29LV008CBTC-70 70 MX29LV008CBTC-90 90 MX29LV008CTTI-55R 55 MX29LV008CTTI-70 70 MX29LV008CTTI-90 90 MX29LV008CBTI-55R 55 MX29LV008CBTI-70 70 MX29LV008CBTI-90 90 MX29LV008CTTC-55Q 55 MX29LV008CTTC-70G 70 MX29LV008CTTC-90G 90 MX29LV008CBTC-55Q 55 MX29LV008CBTC-70G 70 MX29LV008CBTC-90G 90 MX29LV008CTTI-55Q 55 MX29LV008CTTI-70G 70 MX29LV008CTTI-90G 90 MX29LV008CBTI-55Q 55 MX29LV008CBTI-70G 70 MX29LV008CBTI-90G 90 P/N:PM1185 MX29LV008C T/B OPERATING STANDBY Current MAX. (mA) Current MAX. (uA ...
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PART NAME DESCRIPTION 008 P/N:PM1185 MX29LV008C T OPTION: G: Lead-free package R: Restricted VCC (3.0V~3.6V) Q: Restricted VCC (3.0V~3.6V) with Lead-free package SPEED: 55: 55ns 70: 70ns 90: 90ns TEMPERATURE RANGE: ...
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PACKAGE INFORMATION P/N:PM1185 MX29LV008C T/B 52 REV. 1.0, JUN. 30, 2005 ...
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REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" 2. Added "Recommended Operating Conditions" P/N:PM1185 MX29LV008C T/B Page P1 P48 53 Date JUN/30/2005 REV. 1.0, JUN. 30, 2005 ...
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... MX29LV008C T/B MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...