MX29SL800CT Macronix International, MX29SL800CT Datasheet

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MX29SL800CT

Manufacturer Part Number
MX29SL800CT
Description
8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE 1.8V ONLY FLASH MEMORY
Manufacturer
Macronix International
Datasheet

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FEATURES
• Extended single - supply voltage range 1.65V to 2.2V
• 1,048,576 x 8/524,288 x 16 switchable
• Single power supply operation
• Fast access time: 90ns
• Low power consumption
• Command register architecture
• Auto Erase (chip & sector) and Auto Program
• Erase suspend/Erase Resume
• Status Reply
GENERAL DESCRIPTION
The MX29SL800C T/B is a 8-mega bit Flash memory
organized as 1M bytes of 8 bits or 512K words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29SL800C T/B is packaged in 48-pin TSOP and
48-ball CSP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
The standard MX29SL800C T/B offers access time as
fast as 90ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the MX29SL800C T/B has separate chip enable
(CE#) and output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29SL800C T/B uses a command register to manage
this functionality. The command register allows for 100%
P/N:PM1224
- 1.8V only operation for read, erase and program
operation
- 12mA maximum active current (10MHz)
- 1uA typical standby current
- Byte/word Programming (12us/18us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase
- Data# polling & Toggle bit for detection of program
and erase operation completion
8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE
1
MX29SL800C T/B
• Ready/Busy# pin (RY/BY#)
• Hardware reset pin (RESET#)
• Sector protection
• CFI (Common Flash Interface) compliant
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
• Package type:
• Compatibility with JEDEC standard
• 10 years data retention
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29SL800C T/B uses a 1.65V~2.2V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
- Provides a hardware method of detecting program or
erase operation completion
- Hardware method to reset the device to reading array
data
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotected allows code changes
in previously locked sectors
- Flash device parameters stored on the device and
provide the host system to access
- T = Top Boot Sector
- B = Bottom Boot Sector
- 48-pin TSOP
- 48-ball CSP
- All Pb-free devices are RoHS Compliant
- Pinout and software compatible with single-power
supply Flash
1.8V ONLY FLASH MEMORY
REV. 1.0, APR. 20, 2006

Related parts for MX29SL800CT

MX29SL800CT Summary of contents

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FEATURES • Extended single - supply voltage range 1.65V to 2.2V • 1,048,576 x 8/524,288 x 16 switchable • Single power supply operation - 1.8V only operation for read, erase and program operation • Fast access time: 90ns • Low ...

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PIN CONFIGURATIONS 48 TSOP (Standard Type) (12mm x 20mm) A15 1 A14 2 A13 3 A12 4 A11 5 A10 WE# 11 RESET# 12 MX29SL800C T/B www.DataSheet4U.com ...

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CSP( Ball Pitch = 0.8 mm), Top View, Balls Facing Down 6 A13 A9 5 WE# 4 RY/BY# 3 www.DataSheet4U.com P/N:PM1224 MX29SL800C T/B A12 A14 A15 A16 A8 A10 A11 Q7 RE ...

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... BLOCK STRUCTURE TABLE 1: MX29SL800CT SECTOR ARCHITECTURE Sector Sector Size Byte Mode Word Mode SA0 64Kbytes 32Kwords SA1 64Kbytes 32Kwords SA2 64Kbytes 32Kwords SA3 64Kbytes 32Kwords SA4 64Kbytes 32Kwords SA5 64Kbytes 32Kwords SA6 64Kbytes ...

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TABLE 2: MX29SL800CB SECTOR ARCHITECTURE Sector Sector Size Byte Mode Word Mode SA0 16Kbytes 8Kwords SA1 8Kbytes 4Kwords SA2 8Kbytes 4Kwords SA3 32Kbytes 16Kwords SA4 64Kbytes 32Kwords www.DataSheet4U.com SA5 64Kbytes 32Kwords SA6 64Kbytes 32Kwords SA7 64Kbytes 32Kwords SA8 64Kbytes 32Kwords ...

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BLOCK DIAGRAM CE# OE# WE# RESET# www.DataSheet4U.com ADDRESS A0-A18 Q0-Q15/A-1 P/N:PM1224 MX29SL800C T/B CONTROL PROGRAM/ERASE INPUT HIGH VOLTAGE LOGIC FLASH ARRAY LATCH AND BUFFER Y-PASS GATE PGM SENSE DATA AMPLIFIER PROGRAM DATA LATCH I/O BUFFER 6 WRITE STATE MACHINE (WSM) ...

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AUTOMATIC PROGRAMMING The MX29SL800C T/B is byte programmable using the Automatic Programming algorithm. The Automatic Pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming ...

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To verify whether or not sector being protected, the sec- tor address must appear on the appropriate highest order address bit (see Table 1 and Table 2). The rest of address bits, as shown in table 3, are don't care. ...

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QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX29SL800C T/B is capable of operating in the CFI mode. This mode all the host system to determine the manu- facturer of the device such as operating parameters and configuration. Two commands ...

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TABLE 4-3. CFI Mode: Device Geometry Data Values (All values in these tables are in hexadecimal) Description Device size (2 N bytes) Flash device interface code (refer to the CFI publication 100) Maximum number of bytes in multi-byte write (not ...

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TABLE 5. MX29SL800C T/B COMMAND DEFINITIONS Command Bus Cycle Addr Reset 1 Read 1 Read Silicon ID Word 4 Byte 4 www.DataSheet4U.com Sector Protect Word 4 Verify Byte 4 Program Word 4 Byte 4 Chip Erase Word 6 Byte 6 ...

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COMMAND DEFINITIONS Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table ...

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REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array ...

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... ID command sequence into the command regis- ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of EAH/22EAH for MX29SL800CT, 6BH/ 226BH for MX29SL800CB. SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS Chip erase is a six-bus cycle operation. There are two " ...

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... TABLE 7. SILICON ID CODE Pins Manufacture code Word VIL Byte Device code Word VIH for MX29SL800CT Byte Device code Word VIH for MX29SL800CB Byte Sector Protection Word X www.DataSheet4U.com Verification Byte X READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to re- trieve data ...

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SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the de- vice to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up command and Au- tomatic Sector Erase command. Upon executing the Automatic Sector Erase command, the ...

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Q7, Q6, or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a ...

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During an Automatic Program or Erase algorithm opera- tion, successive read cycles to any address cause Q6 to toggle. The system ...

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If this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still func- tional and may be used for the program or erase ...

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Q3 Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. DATA# polling and Toggle Bit are valid after the initial sector ...

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Q0 for the protected sector. CHIP UNPROTECTED The MX29SL800C T/B also features the chip unprotected mode, so that all sectors are unprotected after chip un- protected is completed to incorporate any changes in the code. It ...

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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -55 Ambient Temperature with Power Applied .... ...

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TABLE 9. DC CHARACTERISTICS Symbol PARAMETER ILI Input Leakage Current ILIT A9, OE#, RESET# Input Leakage Current ILO Output Leakage Current ICC1 VCC Active Read Current www.DataSheet4U.com ICC2 VCC Active write Current ICC3 VCC Standby Current ICC4 VCC Standby Current ...

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AC CHARACTERISTICS TA = -40 TABLE 10. READ OPERATIONS SYMBOL PARAMETER tRC Read Cycle Time (Note 1) tACC Address to Output Delay tCE CE# to Output Delay tOE OE# to Output Delay www.DataSheet4U.com tDF OE# High to Output Float (Note1) ...

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SWITCHING TEST CIRCUITS DEVICE UNDER www.DataSheet4U.com SWITCHING TEST WAVEFORMS VCC 0V AC TESTING: Inputs are driven at VCC for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. P/N:PM1224 MX29SL800C T/B ...

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FIGURE 1. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE# VIL www.DataSheet4U.com VIH WE# VIL VIH OE# VIL HIGH Z VOH Outputs VOL VIH RESET# VIL P/N:PM1224 MX29SL800C T/B tRC ADD Valid tACC tCE tOE tOEH tACC tOH DATA Valid ...

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AC CHARACTERISTICS TA = -40 TABLE 11. Erase/Program Operations Parameter Std. Description tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time www.DataSheet4U.com tDS Data Setup Time tDH Data Hold Time tOES Output Enable Setup Time ...

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AC CHARACTERISTICS TA = -40 TABLE 12. Alternate CE# Controlled Erase/Program Operations Parameter Std. Description tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time www.DataSheet4U.com tDH Data Hold Time tOES Output ...

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FIGURE 2. COMMAND WRITE TIMING WAVEFORM VCC 1.8V VIH Addresses VIL VIH WE# VIL www.DataSheet4U.com tOES CE# VIH VIL OE# VIH VIL VIH Data VIL P/N:PM1224 MX29SL800C T/B ADD Valid tAH tAS tWP tCWC tCS tCH tDS tDH DIN 29 ...

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AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional verification by external control are not re- quired because these operations are executed automati- cally by internal control circuit. Programming comple- tion can be verified ...

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FIGURE 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART www.DataSheet4U.com Increment Address P/N:PM1224 MX29SL800C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? ...

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FIGURE 5. CE# CONTROLLED PROGRAM TIMING WAVEFORM 555 for program 2AA for erase Address WE# www.DataSheet4U.com OE# CE# Data tRH RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. 2.Figure indicates the last two ...

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AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is verified automatically by internal control circuit. Erasure completion can be veri- fied by DATA# polling and toggle bit checking after ...

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FIGURE 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART www.DataSheet4U.com P/N:PM1224 MX29SL800C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H ...

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AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector indicated by A12 to A18 are erased. External erase verify is not required because data are verified automatically by internal control circuit. Erasure comple- tion can be verified by DATA# polling and toggle bit ...

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FIGURE 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART www.DataSheet4U.com P/N:PM1224 MX29SL800C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H ...

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FIGURE 10. ERASE SUSPEND/ERASE RESUME FLOWCHART www.DataSheet4U.com Note the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times, then the delay time must be put into consideration. 2. Delay timing: ...

Page 38

FIGURE 11. IN-SYSTEM SECTOR PROTECT/UNPROTECTED TIMING WAVEFORM (RESET# Control) VID VIH RESET# SA, A6 A1, A0 www.DataSheet4U.com Data 1us CE# WE# OE# Note: When sector protect, A6=0, A1=1, A0=0. When chip unprotect, A6=1, A1=1, A0=0. P/N:PM1224 MX29SL800C T/B Valid* Sector ...

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FIGURE 12. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control www.DataSheet4U.com 10. 10.5V 3V OE# WE# CE# Data A18-A12 P/N:PM1224 MX29SL800C T/B tVLHT tVLHT tWPP 1 tOESP Sector Address 39 Verify tVLHT 01H F0H tOE REV. 1.0, ...

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FIGURE 13. SECTOR PROTECTION ALGORITHM (A9, OE# Control) www.DataSheet4U.com PLSCNT=32? Device Failed P/N:PM1224 MX29SL800C T/B START Set Up Sector Addr PLSCNT=1 OE#=VID, A9=VID, CE#=VIL A6=VIL Activate WE# Pulse Time Out 150us Set WE#=VIH, CE#=OE#=VIL A9 should remain VID Read from ...

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FIGURE 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID www.DataSheet4U.com Increment PLSCNT PLSCNT=25? Device failed P/N:PM1224 MX29SL800C T/B START PLSCNT=1 RESET#=VID Wait 1us First Write Cycle=60H Yes Set up sector address Write 60H to sector address with A6=0, A1=1, A0=0 Wait ...

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FIGURE 15. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET#=VID www.DataSheet4U.com Increment PLSCNT PLSCNT=1000? Device failed P/N:PM1224 MX29SL800C T/B START PLSCNT=1 RESET#=VID Wait 1us First Write Cycle=60H ? Yes All sector protected? Yes Set up first sector address Chip unprotect : write ...

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FIGURE 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control) A1 10.5V VCC A9 A6 www.DataSheet4U.com 10.5V VCC OE# WE# CE# Data A18-A12 Notes: tVLHT (Voltage transition time)=4us min. tWPP1 (Write pulse width for sector protect)=100ns min, 10us(Typ.) tWPP2 (Write ...

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FIGURE 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control) www.DataSheet4U.com Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM1224 MX29SL800C T/B START Protect All Sectors PLSCNT=1 Set OE#=A9=VID CE#=VIL,A6=1 Activate WE# ...

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WRITE OPERATION STATUS FIGURE 18. DATA# POLLING ALGORITHM www.DataSheet4U.com NOTE : 1.VA=Valid address for programming P/N:PM1224 MX29SL800C T/B Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? Yes Read Q7~Q0 Add.=VA Yes Q7 = ...

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FIGURE 19. TOGGLE BIT ALGORITHM www.DataSheet4U.com P/N:PM1224 MX29SL800C T/B Start Read Q7-Q0 Read Q7-Q0 (Note 1) NO Toggle Bit Q6 = Toggle ? YES NO Q5= 1? YES Read Q7~Q0 Twice (Note 1,2) NO Toggle bit Q6= Toggle? YES Program/Erase ...

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FIGURE 20. DATA# Polling Timings (During Automatic Algorithms) Address CE# tCH www.DataSheet4U.com OE# tOEH WE# DQ7 Q0-Q6 tBUSY RY/BY# NOTES: 1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read ...

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FIGURE 21. Toggle Bit Timings (During Automatic Algorithms) Address CE# tCH www.DataSheet4U.com OE# tOEH WE# High Z Q6/Q2 tBUSY RY/BY# NOTES: 1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read ...

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TABLE 13. AC CHARACTERISTICS Parameter Std Description tREADY1 RESET# PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP RESET# Pulse Width (During Automatic ...

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AC CHARACTERISTICS TABLE 14. WORD/BYTE CONFIGURATION (BYTE#) Parameter Description Std tELFL/tELFH CE# to BYTE# Switching Low or High tFLQZ BYTE# Switching Low to Output HIGH Z tFHQV BYTE# Switching High to Output Active www.DataSheet4U.com FIGURE 23. BYTE# TIMING WAVEFORM FOR ...

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FIGURE 24. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from word mode to byte mode) CE# OE# www.DataSheet4U.com BYTE# Q0~Q14 Q15/A-1 FIGURE 25. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS CE# WE# BYTE# P/N:PM1224 MX29SL800C T/B tELFH DOUT (Q0-Q14) DOUT ...

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TABLE 15. TEMPORARY SECTOR UNPROTECTED Parameter Std. Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotected Note: Not 100% tested www.DataSheet4U.com FIGURE 26. TEMPORARY SECTOR UNPROTECTED TIMING DIAGRAM 10.5V RESET ...

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FIGURE 28. TEMPORARY SECTOR UNPROTECTED ALGORITHM www.DataSheet4U.com P/N:PM1224 MX29SL800C T/B Start RESET# = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET# = VIH Temporary Sector Unprotect Completed(Note 2) Note : 1. All protected sectors are temporary unprotected. ...

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FIGURE 29. ID CODE READ TIMING WAVEFORM VCC 1.8V VID ADD VIH A9 VIL VIH ADD A0 VIL www.DataSheet4U.com VIH A1 VIL ADD VIH A2-A8 A10-A18 VIL CE# VIH VIL VIH WE# VIL VIH OE# VIL VIH DATA VIL Q0-Q15 ...

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RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) ...

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TABLE 16. ERASE AND PROGRAMMING PERFORMANCE (1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time www.DataSheet4U.com Erase/Program Cycles Note: 1. Not 100% Tested, Excludes external system level over head. 2. Typical values ...

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... ORDERING INFORMATION PART NO. ACCESS TIME (ns) MX29SL800CTTC-90 MX29SL800CBTC-90 MX29SL800CTXBC-90 www.DataSheet4U.com MX29SL800CBXBC-90 MX29SL800CTXEC-90 MX29SL800CBXEC-90 MX29SL800CTXHC-90 MX29SL800CBXHC-90 MX29SL800CTTI-90 MX29SL800CBTI-90 MX29SL800CTXBI-90 MX29SL800CBXBI-90 MX29SL800CTXEI-90 MX29SL800CBXEI-90 MX29SL800CTXHI-90 MX29SL800CBXHI-90 P/N:PM1224 MX29SL800C T/B OPERATING Current MAX. (mA) Current MAX. (uA ...

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PART NAME DESCRIPTION 800 www.DataSheet4U.com P/N:PM1224 MX29SL800C T OPTION: G: Lead-free package blank: normal SPEED: 90: 90ns TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: T: ...

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PACKAGE INFORMATION www.DataSheet4U.com P/N:PM1224 MX29SL800C T/B 59 REV. 1.0, APR. 20, 2006 ...

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P/N:PM1224 MX29SL800C T/B 60 REV. 1.0, APR. 20, 2006 ...

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P/N:PM1224 MX29SL800C T/B 61 REV. 1.0, APR. 20, 2006 ...

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P/N:PM1224 MX29SL800C T/B 62 REV. 1.0, APR. 20, 2006 ...

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REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" title www.DataSheet4U.com P/N:PM1224 MX29SL800C T/B Page P1 63 Date APR/20/2006 REV. 1.0, APR. 20, 2006 ...

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... MX29SL800C T/B MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...

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