U4091BM TEMIC Semiconductors, U4091BM Datasheet - Page 16

• Manufacturer Part Number: U4091BM
• Description: Programmable Telephone Audio Processor
• Manufacturer: TEMIC Semiconductors

Analog-to-Digital Converter ADC
This circuit is a 7-bit successive approximation analog-
to-digital converter in switched capacitor technique. An
internal bandgap circuit generates a 1.25-V reference
voltage
1LSB = 19.5 mV. The possible input voltage at ADIN is
0 to 2.48 V.
The ADC needs an SOC (Start Of Conversion) signal. In
the ‘High’ phase of the SOC signal, the ADC is reset.
50
signal, the ADC generates an EOC (End Of Conversion)
signal which indicates that the conversion is finished. The
rising edge of EOC generates an interrupt at the INT
output. The result can be read out by the serial bus.
Voltages higher than 2.45 V have to be divided. The
signal which is connected to the ADC is determined by
5 bits: ADC0, ADC1, ADC2, ADC3 and NWT.
TLDR/TLDT measuring is possible relative to a preced-
ing reference measurement. The current range of IL can
be doubled by ADCR. If ADCR is ‘High’, S has the value
0.5, otherwise S = 1.
The source impedance at ADIN must be lower than
250 k
Accuracy: 1 LSB + 3%
Table 2. Input selection AD converter
U4091BM
16 (29)
m
s after the beginning of the ‘Low’ phase of the SOC
W
D = measured digital word (0 < = D < = 127)
S = programmable gain 0.5 or 1
Vp = peak value of the measured signal
.
16–31
which
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
is
the
equivalent
ADC[1:4]
1XXXX
00000
00001
00010
00100
00101
01000
01001
01010
00011
00110
00111
01011
01100
01101
01110
01111
Target Specification
of
1
OFF
IL
ADIN extern
VB
VMPS
VMP
TLDR
TLDT
free
SAO1
Offcan1
Offcan2
Offcan3
free
free
free
NWT (TLDR)
MSB.
EOC
SOC
IL 20mV/(1mA S)
8 (TLDR–REF)
8 (TLDT–REF)
0.4 VMPS
0.75 VMP
0.4 SAO1
0.4 OFF1
0.4 OFF2
0.4 OFF3
0.4 VB
I1 = S
V2 = 2.5 V
V3 = (2.5 V / 0.4)
V4 = (2.5 V / 0.4)
V5 = (2.5 V / 0.75)
V6 = 8
V7 = 8
V4 = (2.5 V / 0.4)
TEMIC internal use
TEMIC internal use
TEMIC internal use
ADIN
Figure 17. ADC input selection
Figure 16. Timing of ADC
127 mA
(Vp – Ref)
(Vp – Ref)
D / 127 (max. 2.5 V)
50 s
Value
D / 127
D / 127
D / 127
D / 127
D / 127
D / 127
D / 127
Rev. A1, 02-Jun-98
ADC
SOC
EOC
MSB
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
14595
14594