fdb603al Fairchild Semiconductor, fdb603al Datasheet

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fdb603al

Manufacturer Part Number
fdb603al
Description
N-channel Logic Level Enhancement Mode Field Effect Transistor
Manufacturer
Fairchild Semiconductor
Datasheet

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_________________________________________________________________________________
Absolute Maximum Ratings
Symbol
V
V
I
P
T
T
THERMAL CHARACTERISTICS
R
R
© 1998 Fairchild Semiconductor Corporation
D
FDP603AL / FDB603AL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
J
L
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low
voltage applications such as DC/DC converters and high
efficiency switching circuits where fast switching, low in-line
power loss, and resistance to transients are needed.
DSS
GSS
D
,T
JC
JA
STG
Parameter
Drain-Source Voltage
Gate-Source Voltage - Continuous
Drain Current
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Total Power Dissipation @ T
- Continuous
- Pulsed
Derate above 25°C
T
C
C
= 25°C unless otherwise noted
= 25°C
(Note 1)
Features
FDP603AL
33 A, 30 V. R
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low R
175°C maximum junction temperature rating.
R
DS(ON)
DS(ON)
-65 to 175
0.33
62.5
±20
100
275
= 0.022
= 0.036
30
33
50
3
G
FDB603AL
@ V
@ V
GS
GS
=10 V
=4.5 V
D
S
DS(ON)
.
April 1998
.
FDP603AL Rev.D
Units
W/°C
°C/W
°C/W
W
°C
°C
V
V
A

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fdb603al Summary of contents

Page 1

... FDP603AL / FDB603AL N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance ...

Page 2

Electrical Characteristics T = 25°C unless otherwise noted) C Symbol Parameter DRAIN-SOURCE AVALANCHE RATINGS W Single Pulse Drain-Source Avalanche Energy DSS I Maximum Drain-Source Avalanche Current AR OFF CHARACTERISTICS BV Drain-Source Breakdown Voltage DSS Breakdown Voltage Temp. Coefficient BV / ...

Page 3

Typical Electrical Characteristics 80 V =10V 8.0 GS 7.0 6 DRAIN-SOURCE VOLTAGE (V) DS Figure 1. On-Region Characteristics. 1 25A D 1 10V GS 1.4 ...

Page 4

Typical Electrical Characteristics 25A 5. GATE CHARGE (nC) g Figure 7. Gate Charge Characteristics. 200 100 10V ...

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