ds1238st-r Maxim Integrated Products, Inc., ds1238st-r Datasheet - Page 9

• Manufacturer Part Number: ds1238st-r
• Description: Ds1238 Micromanager
• Manufacturer: Maxim Integrated Products, Inc.

POWER SWITCHING Figure 9
Note: If freshness on the DS1238 is not used,
and V
TIMING DIAGRAMS
This section provides a description of the timing diagrams shown in Figure 10 and Figure 11. Figure 10
illustrates the relationship for power down. As V
the processor is notified of an impending power failure via an active
to save critical data in nonvolatile SRAM. As the power falls further, V
monitor trip point. When V
brought high to write-protect the RAM. When the V
Figure 11 shows the power-up sequence. As V
reset occurs as well as an
maintained for the standard t
will occur. If the processor does not issue an
RST are provided to illustrate these possibilities.
BAT01
for system use.
CC
RPU
NMI
reaches V
timeout period . At a later time, if the IN pin falls below V
. Although the
CCTP
PF
, and active RST and
ST
on the DS1336 may be tied to OUT1. This will free IN4, OUT4,
CC
, a watchdog reset will also occur. The second
CC
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slews above V
NMI
falls, the IN pin voltage drops below V
CC
reaches V
may be short due to slew rates, reset will be
BAT
BAT
RST
, a power-fail is issued via the PF pin.
, the PF pin is deactivated. An active
NMI
are given. At this time,
. This gives the processor time
CC
crosses V
CCTP
TP
TP
. As a result,
, a new
, the power
NMI
CEO
DS1238
NMI
and
is