74HCT109D,653 NXP Semiconductors, 74HCT109D,653 Datasheet - Page 2

• Manufacturer Part Number: 74HCT109D,653
• Description: IC FLIP FLOP JK TYPE DUAL 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr
• Type: JK Typer

Specifications of 74HCT109D,653

• Output Type: Differential
• Package / Case: 16-SOIC (3.9mm Width)
• Function: Set(Preset) and Reset
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 55MHz
• Delay Time - Propagation: 13ns
• Trigger Type: Positive Edge
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: HCT
• Logic Type: J-K Positive Edge Triggered Flip Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 17 ns
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4577-2; 74HCT109D-T; 74HCT109D-T; 933714960653

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT109 are dual positive-edge triggered, JK
flip-flops with individual J, K inputs, clock (CP) inputs, set
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
1997 Nov 25
t
f
C
C
PHL
max
J, K inputs for easy D-type flip-flop
Toggle flip-flop or “do nothing” mode
Output capability: standard
I
I
PD
Dual JK flip-flop with set and reset;
positive-edge trigger
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
SYMBOL
CC
PD
= input frequency in MHz
L
category: flip-flops
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
2
= 25 C; t
V
f
o
CC
propagation delay
maximum clock frequency
input capacitance
power dissipation
) = sum of outputs
capacitance per flip-flop
2
nCP to nQ, nQ
nS
nR
D
D
f
r
i
to nQ, nQ
to nQ, nQ
= t
PARAMETER
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
f
o
) where:
1.5 V.
notes 1 and 2
C
V
CC
L
= 15 pF;
= 5 V
2
.
(S
outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation.
The JK design allows operation as a D-type flip-flop by
tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
CONDITIONS
D
D
) and reset (R
in W):
D
) inputs; also complementary Q and Q
15
12
12
75
20
3.5
HC
TYPICAL
74HC/HCT109
Product specification
17
14
15
61
3.5
22
HCT
ns
ns
ns
MHz
pF
pF
UNIT