isla118p50 Intersil Corporation, isla118p50 Datasheet

isla118p50

Manufacturer Part Number

isla118p50

Description

8-bit, 500msps A/d Converter

Manufacturer

Intersil Corporation

Datasheet

1.ISLA118P50.pdf (35 pages)

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8-Bit, 500MSPS A/D Converter

ISLA118P50

The ISLA118P50 is a low-power, high-performance,

500MSPS analog-to-digital converter designed with

Intersil’s proprietary FemtoCharge® technology on a

standard CMOS process. The ISLA118P50 is part of a

pin-compatible portfolio of 8, 10 and 12-bit A/Ds. This

device an upgrade of the KAD551XP-50 product family

and is pin similar.

The device utilizes two time-interleaved 250MSPS unit

A/Ds to achieve the ultimate sample rate of 500MSPS. A

single 500MHz conversion clock is presented to the

converter, and all interleave clocking is managed

internally. The proprietary Intersil Interleave Engine

(I2E) performs automatic fine correction of offset, gain,

and sample time skew mismatches between the unit

A/Ds to optimize performance. No external interleaving

algorithm is required.

A serial peripheral interface (SPI) port allows for

extensive configurability of the A/D. The SPI also controls

the interleave correction circuitry, allowing the system to

issue continuous calibration commands as well as

configure many dynamic parameters.

Digital output data is presented in selectable LVDS or

CMOS formats. The ISLA118P50 is available in a

72-contact QFN package with an exposed paddle.

Performance is specified over the full industrial

temperature range (-40°C to +85°C).

Block Diagram

March 30, 2010

FN7565.0

CLKN

CLKP

VINN

VINP

VCM

SHA

Gain/ Offset/ Skew

Adjustments

VREF

MANAGEMENT

250MSPS

1.25V

CLOCK

8 -BIT

ADC

VREF

–

I2E

CONTROL

SPI

CORRECTION

DIGITAL

ERROR

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

CLKOUTN

D[7:0]P

D[7:0]N

ORP

ORN

OUTFMT

CLKOUTP

OUTMODE

Features

• 1.15GHz Analog Input Bandwidth

• 90fs Clock Jitter

• Automatic Fine Interleave Correction Calibration

• Multiple Chip Time Alignment Support via the

• Programmable Gain, Offset and Skew control

• Over-Range Indicator

• Selectable Clock Divider: ÷1 or ÷2

• Clock Phase Selection

• Nap and Sleep Modes

• Two’s Complement, Gray Code or Binary Data

• DDR LVDS-Compatible or LVCMOS Outputs

• Programmable Test Patterns and Internal

Applications

• Radar and Electronic/Signal Intelligence

• Broadband Communications

• High-Performance Data Acquisition

Pin-Compatible Family

Key Specifications

• SNR = 49.9dBFS for f

• SFDR = 68dBc for f

• Total Power Consumption = 428mW

ISLA112P50

ISLA110P50

ISLA118P50

Synchronous Clock Divider Reset

Format

Temperature Sensor

All other trademarks mentioned are the property of their respective owners.

Intersil (and design) is a registered trademark of Intersil Americas Inc.

MODEL

RESOLUTION

= 190MHz (-1dBFS)

(MSPS)

SPEED

500

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