isl3874 Intersil Corporation, isl3874 Datasheet
isl3874
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isl3874 Summary of contents
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... I/O drivers. Additional firmware functions specific to access point applications are also available. The ISL3874 has on-board A/Ds and D/A for analog I and Q inputs and outputs, for which the HFA3783 IF QMODEM is recommended. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with Complementary Code Keying to provide a variety of data rates ...
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... HOST INTERFACE MICRO- PROGRAMMED MAC ENGINE WEP ENGINE ON-CHIP ROM MEMORY CONTROLLER ON-CHIP RAM MEDIUM ACCESS CONTROLLER ADDRESS DATA SELECT EXTERNAL SRAM AND FLASH MEMORY 2 ISL3874 ISL3874 1 1 AGC 7 CTL 6 DEMOD 6 PHY DATA I/O INTERFACE (MDI) I/O SERIAL CONTROL (MMI) 6 MOD ALC 6 ...
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... ISL3874 Signal Descriptions PIN PIN NAME NUMBER PIN I/O TYPE HAD31 A8 5V Tol, CMOS, BiDir PCI address/data bus bit 31. These signals make up the multiplexed PCI address and data bus on HAD30 A9 5V Tol, CMOS, BiDir PCI address/data bus bit 30. HAD29 C8 5V Tol, CMOS, BiDir PCI address/data bus bit 29. ...
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... Tol, CMOS, BiDir PCI device select. The ISL3874 asserts HDEVSEL to claim a PCI cycle as the target device HPERR D16 5V Tol, CMOS, BiDir PCI bus parity. In all PCI bus read and write cycles, the ISL3874 calculates even parity across the HGNT C7 5V Tol, CMOS, ST ...
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... MD1 R1 CMOS, BiDir, 2mA, 50K Pull Down MD0 P2 CMOS, BiDir, 2mA, 50K Pull Down 5 ISL3874 TABLE 2. MEMORY INTERFACE PINS PIN I/O TYPE MBUS Address Bit 19, needed to address between 512KB and 1MB of data store MBUS Address Bit 18 MBUS Address Bit 17 MBUS Address Bit 16 ...
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... P8 CMOS BiDir, 2mA, 50K Pull Up PL7 T6 CMOS BiDir, 2mA, 50K Pull Down 6 ISL3874 TABLE 2. MEMORY INTERFACE PINS (Continued) PIN I/O TYPE MBUS Lower Byte Enable. Asserted when accessing the low-order byte of x16 memory devices that use the JEDEC 5-wire control interface. Memory Output Enable; asserted on memory reads Low (or only) Byte Memory Write Enable ...
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... R14 O TXQ T14 O 7 ISL3874 TABLE 4. SERIAL EEPROM PORT CONNECTIONS PIN I/O TYPE SCLK, serial clock for serial EEPROM devices Serial Data Out (SD) used on serial EEPROM devices which require three and four wire interfaces, example: AT45DB011 Serial Data In (MISO) used on serial EEPROM devices, Used in four wire serial devices only ...
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... M16, K13 ST = Schmitt Trigger (Hysteresis Three-State. Signals ending with “-” are active low. 8 ISL3874 TABLE 8. MISCELLANEOUS CONTROL PORT PINS Global Reset for MAC, Active LOW CS used for Chip Select Output for Serial Devices which have a 4 wire interface like the AST45DB011 and also serial data on two wire devices like the 24C08 ...
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... MA (17..0) Hold from MWE_ Rising Edge RAMCS _ Hold from MWE_ Rising Edge MD (15..0) Setup to MWE_ Rising Edge MD (15..0) Hold from MWE_ Rising Edge 9 ISL3874 Thermal Information Thermal Resistance (Typical, Note 1) +0.5V BGA Package ...
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... Setup Time Before HPCLK Valid Hold Time After HPCLK High BASEBAND SIGNALS Full Scale Input Voltage (V ) P-P Input Bandwidth (-0.5dB) Input Capacitance Input Impedance (DC) FS (Sampling Frequency) Waveforms ADDRESS MA(17..1) RAMCS MOE t S2 MD(15..0) 10 ISL3874 SYMBOL t CYC CYC ...
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... Waveforms (Continued) ADDRESS MA(17..1) RAMCS MWE MD(15..0) SYNTHCLK SYNLE SPCSPWR t D1 SYNTHDATA 1.5V HPCLK PCI OUTPUT PCI INPUT 11 ISL3874 FIGURE 2. MAC EXTERNAL MEMORY WRITE TIMING CYC t D2 D[n] D[n -1] D[n -2] D[2] FIGURE 3. SYNTHESIZER CYC FIGURE 4. HPCLK TIMING WAVEFORM t V VALID ...
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... MD0..15 MA1..17 NVCS MOE MWEL MA0/MWEH RAMCS FIGURE 6. 8 BIT MEMORY INTERFACE ISL3874 MA1..17 MD0..15 NVCS MA0/MWEH MLBE RAMCS MOE MWEL FIGURE 7. 16-BIT MEMORY INTERFACE 12 ISL3874 SRAM 128Kx8 MD0..7 MA1.. SRAM 128Kx16 ADDR(0..16) DATA(0..15 FLASH 128Kx8 MD0..7 MA0 ...
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... An access point application could make use of the full address space of the device with 4Mbytes organized 16. The ISL3874 supports 8 or 16-bit code space, and 8 or 16-bit data space. Code space is typically populated with the least expensive Flash memory available, usually an 8-bit device. ...
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... The PCI core has two sets of configuration registers. One set is read-only and configured to default values or set up by ISL3874 firmware on reset. This set is used by the host to determine what type of card this is, and what drivers need to be loaded. The other set is the host configuration registers. ...
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... PCI read or write system call request length. PCI requests for greater than word length (16 bits) will have the upper bits zeroed. PCI Specific Implementation The ISL3874 host side memory space is not intended to be written in a sequential manner so burst operations are not supported. Only memory read, memory write, and configuration cycles are supported in target mode ...
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... HPME - Power Management Event Output. HPME provides output for PME signals. Register Interface The logical view of the ISL3874 from the host is a block of 32 word wide registers. These appear in IO space starting at the base address determined by the socket controller. There are three types of registers. ...
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... Hardware buffer chaining provides high performance while reading and writing buffers. Data is transferred between the host driver and the ISL3874 by writing or reading a single register location (The Buffer Access Path, or BAP). Each access increments the address in the buffer memory. ...
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... Power On Reset Configuration Power On Reset is issued to the ISL3874 with the GRESET pin or via the soft reset bit, SRESET, in the Configuration Option Register (COR, bit 7). The MD[15:8] pin values are sampled during GRESET. ...
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... The I/Q A/D clock, samples at twice the chip rate with a nominal sampling rate of 22MHz. The interface specifications for the I and Q A/Ds are listed in Table 14. The ISL3874 is designed coupled to the HFA3783. The voltages applied to pin 16, V the references for the internal I and Q A/D converters. In ...
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... DC coupled and digitally filtered. 11MHz - Test Port 2 - The ISL3874 provides the capability to access a number internal signals and/or data through the Test port, pins TEST 22MHz - 7:0. The test port is programmable through configuration register (CR34). Any signal on the test port can also be read from configuration register (CR50) via the serial control port ...
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... Header/Packet Description The ISL3874 is designed to handle packetized Direct Sequence Spread Spectrum (DSSS) data transmissions. The ISL3874 generates its own preamble and header information. It uses two packet preamble and header configurations. The first is backwards compatible with the existing IEEE 802.11-1997 1 and 2Mbps modes and the second is the optional shortened mode which maximizes throughput at the expense of compatibility with legacy equipment ...
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... See IEEE STD 802.11 for definition of the other bits. Bit 2 is used by the ISL3874 to indicate that the carrier reference and the bit timing references are derived from the same oscillator (locked oscillators). ...
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... The modulator can support date rates 5.5 and 11Mbps. The programming details to set up the modulator are given at the introductory paragraph of this section. The ISL3874 utilizes Quadraphase (I/Q) modulation at baseband for all modulation modes. In the 1Mbps DBPSK mode, the I and Q Channels are connected together and driven with the output of the scrambler and differential encoder ...
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... Carrier Sense Multiple Access (CSMA) networking scheme. The Clear Channel Assessment (CCA) monitors the environment to determine when it is clear to ODD SYMBOLS transmit. The CCA circuit in the ISL3874 can be programmed to PHASE CHANGE be a function of RSSI (energy detected on the channel), CS1, (+j ) SQ1, or various combinations ...
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... The AGC system consists of the 3 chips handling the receive signal, the downconverter HFA3683, the IF to baseband converter HFA3783, and the baseband processor (BBP) section of the ISL3874. The AGC loop (Figure 11) is digitally controlled by the BBP. Basically it operates as follows: Initially, the receiver is set for high gain. The percent of time ...
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... RF chip to switch from high gain to low gain. RX_IF_Det is the input to the ISL3874 chip from the HFA3783 which is transferred to ifCompDet on the HFA3874. RX_RF_AGC is the output of the ISL3874 chip and ‘1’ is high gain, ‘0’ is low gain. Demodulator Description The receiver portion of the baseband processor, performs A/D conversion and demodulation of the spread spectrum signal ...
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... PN Correlators Description There are two types of correlators in the ISL3874 baseband processor. The first is a parallel matched filter correlator that correlates for the Barker sequence used in preamble, header, and PSK data modes. This Barker code correlator is designed to handle BPSK spreading with carrier offsets up to 50ppm and 11 chips per symbol ...
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... RATE T0 CORRELATOR OUTPUT IS THE RESULT OF CORRELATING THE PN SEQUENCE WITH THE RECEIVED SIGNAL 28 ISL3874 error is made the whole packet is discarded anyway, so the error extension property has no effect on the packet error rate. It should be taken into account if a forward error correction scheme is contemplated. Descrambling is self synchronizing and is done by a polynomial division using a prescribed polynomial ...
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... RXQ A/D 6 COHERENT TIMING INTEGRATOR ANTSEL ANTENNA SWITCH ANTSEL CONTROL TIMING GENERATOR MCLK RESET RX_PE FIGURE 18. DSSS BASEBAND PROCESSOR, RECEIVE SECTION 29 ISL3874 GND (ANALOG) V (DIGITAL) DD CLEAR CHANNEL ASSESSMENT/ SIGNAL QUALITY CMF TRAINING 8 PEAK EXTRACT. 8 SYMBOL TRACKING EQUAL. NCO CCK BIAS CORREL ...
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... The symbol clock is tracked by a sample interpolator that can adjust the sample timing forwards and backwards by 72 increments of 1/8th chip. This approach means that the ISL3874 can only track an offset in timing for a finite interval before the limits of the interpolator are reached. Thus, continuous demodulation is not possible. ...
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... CCK modes. The losses in both figures include RF and IF radio losses; they do not reflect the ISL3874 losses alone. The ISL3874 baseband processing losses from theoretical are, by themselves, a small percentage of the overall loss. The PRISM demodulator performs with an implementation loss of less than 4dB from theoretical in a AWGN environment with low phase noise local oscillators ...
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... FIGURE 23. ED THRESHOLD vs SNR 1Mbps A Default Register Configuration PER The registers in the ISL3874 are addressed with 7-bit numbers MEAN where the lower 1 bit of an 8-bit hexadecimal address is left as STDDEV unused. This results in the addresses being in increments of 2. The data is transmitted as either DBPSK, DQPSK, or CCK depending on the configuration chosen ...
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... For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd., Mail Stop 53-204 Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 33 ISL3874 A V192.14x14 192 BALL PLASTIC BALL GRID ARRAY PACKAGE SYMBOL ...