SSTUA32S865 NXP Semiconductors, SSTUA32S865 Datasheet
SSTUA32S865
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SSTUA32S865 Summary of contents
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... RDIMM applications Rev. 02 — 16 March 2007 1. General description The SSTUA32S865 is a 1.8 V 28-bit register specifically designed for use on two rank by four (2R modules similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs ...
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... MT/s to 667 MT/s high-density (for example, 2 rank by 4) DDR2 registered DIMMs I DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality 4. Ordering information Table 1. Ordering information Type number Solder process SSTUA32S865ET/G Pb-free (SnAgCu solder ball compound) SSTUA32S865ET SnPb solder ball compound SSTUA32S865_2 Product data sheet 1.8 V DDR2-667 registered buffer with parity Package ...
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... NXP Semiconductors 5. Functional diagram VREF PARIN D0 D21 DCS0 CSGATEEN DCS1 DCKE0, 2 DCKE1 DODT0, 2 DODT1 RESET CK CK Fig 1. Functional diagram of SSTUA32S865 SSTUA32S865_2 Product data sheet 1.8 V DDR2-667 registered buffer with parity (CS ACTIVE) PARITY D Q GENERATOR AND 22 R CHECKER ...
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... Product data sheet 1.8 V DDR2-667 registered buffer with parity SSTUA32S865ET/G SSTUA32S865ET ball A1 index area 002aab387 Transparent top view Rev. 02 — 16 March 2007 SSTUA32S865 11 © NXP B.V. 2007. All rights reserved ...
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... VDDL GND VDDL VDDL VDDR GND VDDL VDDL GND PTYERR MCH Q3B Q12B n.c. MCH Q3A Q12A Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity Q21A Q19A Q18A Q17B Q21B Q19B Q18B QODT0B QODT1B GND GND Q20B GND ...
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... Chip Select input is LOW during the rising edge of the clock. When LOW, the D0 to D21 inputs will be latched and redriven on every rising edge of the clock. Rev. 02 — 16 March 2007 SSTUA32S865 © NXP B.V. 2007. All rights reserved ...
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... Input reference voltage for the SSTL_18 inputs. Two pins nominal (internally tied together) are used for increased reliability. Power supply voltage. Power supply voltage. Ground. Ball present but not connected to die. Rev. 02 — 16 March 2007 SSTUA32S865 © NXP B.V. 2007. All rights reserved ...
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... X or floating floating floating Inputs floating X or floating Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity Outputs Dn, DODTn, Qn QCS0 QCS1 DCKEn ...
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... As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUA32S865 ensures that the outputs remain LOW, thus ensuring no glitches on the output. ...
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... LOW quickly except the PTYERR output, which will be floated (and will normally default HIGH by their external pull-up). 7.3.4 Power-up sequence The reset function for the SSTUA32S865 is similar to that of the SSTU32864 except that the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive clock cycles. ...
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... V DDR2-667 registered buffer with parity PDM PDMSS PHL CK to PTYERR HIGH or LOW Rev. 02 — 16 March 2007 SSTUA32S865 PHL PLH CK to PTYERR 002aaa983 © NXP B.V. 2007. All rights reserved ...
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... PDMSS Output signal is dependent on the prior unknown event Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity PHL PLH CK to PTYERR HIGH or LOW © NXP B.V. 2007. All rights reserved. 4 002aaa984 ...
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... Fig 6. RESET switches from HIGH to LOW SSTUA32S865_2 Product data sheet t INACT t PHL RESET PLH RESET to PTYERR HIGH, LOW, or Don't care . INACT(max) Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity HIGH or LOW © NXP B.V. 2007. All rights reserved. 002aaa985 ...
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... HIGH”. Fig 7. Parity logic diagram SSTUA32S865_2 Product data sheet 1.8 V DDR2-667 registered buffer with parity Section 7 “Functional description” Rev. 02 — 16 March 2007 SSTUA32S865 LATCHING AND (1) RESET FUNCTION 002aaa417 and Figure 4 “RESET © NXP B.V. 2007. All rights reserved. QnA QnB ...
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... V ref [1] data inputs (Dn) - [1] data inputs (Dn) V ref [1] data inputs (Dn) - [2] RESET 0.65 [2] RESET - CK, CK 0.675 CK, CK 600 - - operating in 0 free air Rev. 02 — 16 March 2007 SSTUA32S865 Min Max 0.5 +2.5 [1] 0.5 +2.5 [ 100 65 +150 2 - 200 - Typ Max - 2.0 V ...
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... One data input switching at half clock frequency duty cycle mA 1 data inputs 250 mV; I ref and CK 0 600 mV; ICR 1 RESET GND 1 Rev. 02 — 16 March 2007 SSTUA32S865 Min Typ Max 1 0 2 ...
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... PARIN after CK and CK after RESET is taken HIGH. ACT(max) INACT(max) Conditions CK and CK to output CK and CK to PTYERR CK and CK to PTYERR from RESET to PTYERR [1][2] CK and CK to output RESET to output Conditions Rev. 02 — 16 March 2007 SSTUA32S865 Min Typ Max Unit - - 450 MHz ...
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... V IH ref 250 mV (AC voltage levels) for differential inputs ref Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity = 50 ; input slew rate = 1 V/ns 0 DUT delay = 350 OUT (1) ...
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... PLH PHL 250 mV (AC voltage levels) for differential inputs ref 250 mV (AC voltage levels) for differential inputs ref Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity V V ICR ref V IL 002aaa374 = V for LVCMOS inputs ...
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... V/ns 0 DUT OUT includes probe and jig capacitance. L output dv_f DUT OUT includes probe and jig capacitance. L dv_r output Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity 20 %, unless otherwise specified test point ( 002aaa377 V ...
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... L LVCMOS RESET 0.5V t PLH output waveform 2 RESET input timing V ICR inputs t HL output waveform 1 to clock inputs Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity 20 %, unless otherwise specified test point ( 002aaa500 ...
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... Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to SSTUA32S865_2 Product data sheet timing V ICR inputs t LH output waveform 2 clock inputs Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity V V i(p-p) ICR 002aaa503 © NXP B.V. 2007. All rights reserved ...
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... 9.1 13.1 0.65 7.15 11.05 0.15 8.9 12.9 REFERENCES JEDEC JEITA - - - - - - Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity detail scale 0.08 0.1 0.1 EUROPEAN PROJECTION SOT802 ISSUE DATE 03-01-29 © NXP B.V. 2007. All rights reserved. ...
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... Solder bath specifications, including temperature and impurities SSTUA32S865_2 Product data sheet 1.8 V DDR2-667 registered buffer with parity Rev. 02 — 16 March 2007 SSTUA32S865 © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 23. Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity Figure 23) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
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... Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity peak temperature © NXP B.V. 2007. All rights reserved. time 001aac844 ...
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... PHL Product data sheet Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity Change notice Supersedes - SSTUA32S865_1 LOW”: changed “t ” to “t ”; changed “t RPHL PHL ” to “ changed Parameter to “pulse width”; moved “CK, CK ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 16 March 2007 SSTUA32S865 1.8 V DDR2-667 registered buffer with parity © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: SSTUA32S865_2 All rights reserved. Date of release: 16 March 2007 ...