TS80C54X2XXX-MCE ATMEL Corporation, TS80C54X2XXX-MCE Datasheet - Page 26
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TS80C54X2XXX-MCE
Manufacturer Part Number
TS80C54X2XXX-MCE
Description
At87c54x2, Ts87c54x2
Manufacturer
ATMEL Corporation
Datasheet
1.TS80C54X2XXX-MCE.pdf
(62 pages)
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26
AT/TS8xC54/8X2
If two interrupt requests of different priority levels are received simultaneously, the request of
higher priority level is serviced. If interrupt requests of the same priority level are received simul-
taneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence.
Table 10-2.
Reset Value = 0X00 0000b
Bit addressable
Number
Bit
EA
7
6
5
4
3
2
1
0
7
Mnemonic
ET2
ET1
EX1
ET0
EX0
Bit
EA
ES
IE Register
IE - Interrupt Enable Register (A8h)
-
6
-
Enable All interrupt bit
own interrupt enable bit.
Reserved
Timer 2 overflow interrupt Enable bit
Serial port Enable bit
Timer 1 overflow interrupt Enable bit
External interrupt 1 Enable bit
Timer 0 overflow interrupt Enable bit
External interrupt 0 Enable bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its
The value read from this bit is indeterminate. Do not set this bit.
Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
ET2
5
ES
4
ET1
3
Description
EX1
2
ET0
1
4431E–8051–04/06
EX0
0
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