sn74ls165n ON Semiconductor, sn74ls165n Datasheet - Page 5

• Manufacturer Part Number: sn74ls165n
• Description: Low Power Schottky
• Manufacturer: ON Semiconductor

DEFINITION OF TERMS:
SETUP TIME (t
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW-to-HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
following the clock transition from LOW-to-HIGH that the
logic level must be maintained at the input in order to ensure
Q
PL OR CP
7
OR Q
CP
CP
P
1
2
7
n
h
s
) — is defined as the minimum time
) — is defined as the minimum time
t
s
1.3 V
t
s(H)
1.3 V
Figure 1.
Figure 3.
1.3 V
t
1.3 V
PHL
t
1/f
h(H)
max
t
s(L)
t
W
t
PLH
1.3 V
1.3 V
1.3 V
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AC WAVEFORMS
SN74LS165
t
1.3 V
h(L)
5
continued recognition. A negative hold time indicates that
the correct logic level may be released prior to the clock
transition from LOW-to-HIGH and still be recognized.
RECOVERY TIME (t
required between the end of the PL pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer loaded Data to the Q outputs.
Q
CP
PL
7
OR Q
PL
7
t
1.3 V
PLH
1.3 V
t
W
rec
) — is defined as the minimum time
t
Figure 4.
W
Figure 2.
1.3 V
1.3 V
1.3 V
1.3 V
t
rec
1.3 V
1.3 V
t
PHL