cs4390 Cirrus Logic, Inc., cs4390 Datasheet
cs4390
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cs4390 Summary of contents
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... P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com Description The CS4390 is a complete stereo digital-to-analog out- put system. In addition to the traditional D/A function, the CS4390 includes a digital interpolation filter followed by an 128X oversampled delta-sigma modulator. The mod- ulator output controls the reference voltage input to an ultra-linear analog low-pass filter ...
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... kHz Fs = 44.1 kHz kHz Normal Operation Power-down Normal Operation Power-down PSRR CS4390 = 20 k differential Min Typ Max - 103 - 101 106 - - 103 - - 106 - - ...
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... MCLK / LRCK = 384 MCLK / LRCK = 256 MCLK / LRCK = 256 t sclkl t sclkh t sclkw t slrd t slrs t sdlrs t sdh SCLK / LRCK = 64 t sclkw t sdlrs MCLK / LRCK = 256 or t sdh MCLK / LRCK = 384 t sdh CS4390 Min Typ Max 1.90 2.0 2. 100 Min Typ Max ...
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... LRCK SCLK SDATA LRCK SDATA *INTERNAL SCLK * The SCLK pin must be terminated to ground. The SCLK pulses shown are internal to the CS4390 slrs sclkl slrd t sdh t sdlrs External Serial Mode Input Timing t t sdlrs sdh Internal Serial Mode Input Timing ...
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... (AGND = 0 V, all voltages with respect to ground.) Symbol Positive Analog VA Positive Digital VD | IND stg (DGND = 0V; all voltages with respect to ground) Symbol Positive Digital VD Positive Analog VA |VA - VD| CS4390 Min Typ Max Unit 2 0 ±10 Min Max Unit -0.3 6.0 V -0.3 6.0 V ...
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... AOUTL- 12 DIF2 CS4390 7 LRCK 9 AOUTL+ SCLK* 10 SDATA 1 DEM0 2 DEM1 AOUTR- 15 MUTE_R 16 MUTE_L 11 AUTO_MUTE AOUTR+ 8 MCLK DGND AGND SCLK must be connected to DGND for operation in Internal SCLK Mode Figure 1. Typical Connection Diagram CS4390 +5V Analog + Analog Conditioning 18 13 Analog Conditioning 14 DS264F1 ...
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... GENERAL DESCRIPTION The CS4390 is a complete stereo digital-to-analog system including 128× digital interpolation, fourth- order delta-sigma digital-to-analog conversion, 128× oversampled one-bit delta-sigma modulator and analog filtering. This architecture provides a high insensitivity to clock jitter. The DAC converts digital data at any input sample rate between 1 and 50 kHz, including the standard audio rates of 48, 44 ...
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... SCLK. For- mats 0, 1, and 2 are 16, 24, and 20-bit versions, re- spectively, and differ only in the number of data bits required. Format 1 in the CS4390 is not com- patible with Format 1 in the CS4329. Formats 3 and 4 are 24-bit left justified, MSB ...
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NOTE: Format 1 is not compatible with CS4329 Figure 3. Digital Input Format 0, 1 and 2. Figure 4. Digital Input Format 3. ...
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Figure 5. Digital Input Format 4. Figure 6. Digital Input Format 5. Figure 7. Digital Input Format 6. ...
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... Serial Clock The serial clock controls the shifting of data into the input data buffers. The CS4390 supports both external and internal serial clock generation modes. External Serial Clock The CS4390 will enter the external serial clock mode more high\low transitions are detect the SCLK pin during any phase of the LRCK period ...
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... CS4390 will reset. Power is applied to the internal voltage reference, the D/A convert- ers, switched-capacitor filters and the DAC will then enter a calibration mode to properly set the common mode bias voltage and minimize the dif- ferential offset. This initialization and calibration sequence requires approximately 2700 cycles of LRCK ...
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... All mode pins which require VD should be connected to pin 6 of the CS4390. All mode pins which require DGND should be con- nected to pin 5 of the CS4390. Pins 4 and 5, AGND and DGND, should be connected together at the CS4390. DGND for the CS4390 should not be con- fused with the ground for the digital section of the (2 ...
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... Hz sine wave which fades from -60 to -120 dBFS. During the 14 fade, the output from the CS4390 is measured and compared to the ideal level. Notice the very close tracking of the output level to the ideal, even at low level inputs. The gradual shift of the plot away from zero at signals levels < ...
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... -120 14k 16k 18k 20k -60 -50 -40 -30 -20 dBFS Figure 15. THD+N vs. Amplitude 2.5k 5k 7.5k 10k 12.5k 15k Hz Figure 17. -20 dBFS FFT -100 -80 -60 -40 dBFS Figure 19. Fade-to-Noise Linearity CS4390 -10 +0 17.5k 20k - ...
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... Analog output connections for the Left channel differential outputs. Nominally 2 Vrms (differential) for full-scale digital input signal. 16 PDIP and SSOP DEM0 DIF0 1 20 DEM1 DIF1 AOUTL AGND AOUTL DGND 5 16 MUTE_L MUTE_R 7 14 LRCK AOUTR MCLK AOUTR SCLK DIF2 10 11 SDATA AUTO-MUTE CS4390 DS264F1 ...
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... Two's complement MSB-first serial data of either 16, 18 bits is input on this pin. The data is clocked into the CS4390 via the SCLK clock and the channel is determined by the LRCK clock. The format for the previous two clocks is determined by the Digital Input Format pins, DIF0, DIF1 and DIF2 ...
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... Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 18 CS4390 DS264F1 ...
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... SSOP PACKAGE DRAWING SIDE VIEW INCHES MIN MAX -- 0.084 0.002 0.010 0.064 0.074 0.009 0.015 0.272 0.295 0.291 0.323 0.197 0.220 0.022 0.030 0.025 0.041 0° 8° END VIEW L SEATING PLANE MILLIMETERS NOTE MIN MAX -- 2.13 0.05 0.25 1.62 1.88 0.22 0.38 2,3 6.90 7.50 7.40 8.20 5.00 5.60 0.55 0.75 0.63 1.03 0° 8° CS4390 ...
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... MIN MAX 0.000 0.210 0.015 0.025 0.115 0.195 0.014 0.022 0.045 0.070 0.008 0.014 0.980 1.060 0.300 0.325 0.240 0.280 0.090 0.110 0.280 0.320 0.300 0.430 0.000 0.060 0.115 0.150 0° 15° CS4390 SIDE VIEW MILLIMETERS MIN MAX 0.00 5.33 0.38 0.64 2.92 4.95 0.36 0.56 1.14 1.78 0.20 0.36 24.89 26.92 7.62 8.26 6.10 7.11 2.29 2.79 7.11 8 ...
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Notes • ...
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