ad55-035z-0reel Analog Devices, Inc., ad55-035z-0reel Datasheet - Page 7

• Manufacturer Part Number: ad55-035z-0reel
• Description: Cmos, 330 Mhz Triple 8-bit High Speed Video Dac
• Manufacturer: Analog Devices, Inc.

Pin Number
1, 2, 14, 15, 25, GND
26, 39, 40
3–10,
16–23,
41–48
11
12
13, 29, 30
24
27, 31, 33
28, 32, 34
35
36
37
38
REV. 0
B0–B7,
R0–R7
Mnemonic
G0–G7,
BLANK
SYNC
V
CLOCK
IOR, IOG, IOB Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These
IOR, IOG, IOB Red, Green, and Blue Current Outputs. These high impedance current sources are capable of
COMP
V
R
PSAVE
AA
REF
SET
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge
of CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should
be connected to either the regular PCB power or ground plane.
Composite Blank Control Input (TTL Compatible). A logic zero on this control input drives the
analog outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the
rising edge of CLOCK. While BLANK is a logical zero, the R0–R7, G0–G7, and B0–B7 pixel
inputs are ignored.
Composite Sync Control Input (TTL Compatible). A logical zero on the SYNC input switches
off a 40 IRE current source. This is internally connected to the IOG analog output. SYNC does
not override any other control or data input; therefore, it should only be asserted during the
blanking interval. SYNC is latched on the rising edge of CLOCK. If sync information is not
required on the green channel, the SYNC input should be tied to logical zero.
Analog Power Supply (5 V ± 5%). All V
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7,
SYNC, and BLANK pixel and control inputs. It is typically the pixel clock rate of the video
system. CLOCK should be driven by a dedicated TTL buffer.
RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly
terminated 75 Ω load. If the complementary outputs are not required, these outputs should be
tied to ground.
directly driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have
similar output loads whether or not they are all being used.
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF
ceramic capacitor must be connected between COMP and V
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V)
A resistor (R
video signal. Note that the IRE relationships are maintained, regardless of the full-scale output
current. The relationship between R
is connected to IOG) is given by:
The relationship between R
The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used,
i.e., SYNC tied permanently low.
Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this
pin is active.
Function
Ground. All GND pins must be connected.
PIN FUNCTION DESCRIPTIONS
IOG mA
R
IOR IOB mA
SET
SET
) connected between this pin and GND controls the magnitude of the full-scale
,
( )
( )
Ω
=
=
11 445
( )
11 444 8
SET
,
,
–7–
and the full-scale output current on IOR, IOG, and IOB is given by:
=
×
7 989 6
.
,
V
×
REF
SET
V
.
REF
and the full-scale output current on IOG (assuming I
( )
V
AA
×
V
( )
V
pins on the ADV7125 must be connected.
/
REF
IOG mA
/
R
( )
V
SET
( )
/
( )(
Ω
R
SET
SYNC being asserted
( )
AA
Ω
.
ADV7125
)
SYNC