ltc2273 Linear Technology Corporation, ltc2273 Datasheet
ltc2273
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ltc2273 Summary of contents
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... P-P JEDEC serial interface for data converters specifi cation (JESD204). The LTC2273/LTC2272 are perfect for demanding applica- tions where it is desirable to isolate the sensitive analog circuits from the noisy digital logic. The AC performance includes a 77.7dB Noise Floor and 100dB spurious free dynamic range (SFDR) ...
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... Analog Input Voltage (Note 3) .......–0. Digital Input Voltage ......................–0. Digital Output Voltage ................ –0.3V to (OV Power Dissipation .............................................2000mW Operating Temperature Range LTC2273C/LTC2272C ............................... 0°C to 70°C LTC2273I/LTC2272I .............................. –40°C to 85°C Storage Temperature Range ................... –65°C to 150°C Digital Output Supply Voltage (OV DD ...
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... IN = 25° 25° 25° 25°C A LTC2273/LTC2272 MIN TYP MAX l 1 1.25 1.5 l –1 1 –3 3 6.7 1 700 LTC2273 LTC2272 MIN TYP MAX MIN TYP 77.6 77.6 75.4 75.4 76.5 77.5 76.5 77.5 l 76.2 77.2 76.2 77.2 75.3 75.3 77.2 77.2 74.5 75.1 74.5 75.1 l 74.2 74.8 74.2 74 ...
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... Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = The denotes the specifi cations which apply over the full operating temperature range, = –1dBFS unless otherwise noted. (Note 25° 25°C A LTC2273 LTC2272 MIN TYP MAX MIN TYP 100 100 100 100 l ...
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... OUT = 25°C. (Note 4) A ≤ 3.465V | ≤ 1mA The = 25°C. (Note 3. – LTC2273/LTC2272 l The denotes the specifi cations which apply over MIN TYP MAX 1.15 1.25 1. denotes the specifi cations which apply over the ...
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... CONV CONV 0.35 110 50 110 2 2.5 t – CONV SU HD CONV 80Msps (LTC2273) or 65Msps (LTC2272) SAMPLE with differential drive. P-P MAX UNITS 3.465 340 1122 mW MAX UNITS 65 MHz ...
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... LAT SC N – – 8 SYNC + Falling Edge to Comma (K28.5) Timing LAT SD K28.5 (x2) K28.5 (x2) SYNC + Rising Edge to Data Timing LTC2273/LTC2272 – 22732 TD01 – 7 K28.5 (x2) K28.5 (x2 – ...
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... FREQUENCY (MHz) LTC2273: SFDR vs Input Level 15MHz, PGA = 0, IN Dither “On” 140 130 120 110 100 –80 –70 –60 –50 –40 –30 –20 –10 ...
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... FREQUENCY (MHz) LTC2273: SFDR vs Input Level 140MHz, PGA = 1, IN Dither “On” 140 130 120 110 100 –80 –70 –60 –50 –40 –30 –20 –10 ...
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... LTC2273: SNR vs Input Frequency 78 76 PGA = 100 200 400 INPUT FREQUENCY (MHz) 22732 G20 LTC2273: SNR and SFDR vs Supply Voltage ( 5.2MHz IN SFDR SNR 2.8 3.0 3.2 3.4 SUPPLY VOLTAGE (V) 22732 G23 LTC2273 Sample Rate, DD 5MHz Sine, –1dBFS ...
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... PGA = 0, IN Dither “On” 140 130 120 110 100 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) LTC2273/LTC2272 V = 3.3V 1.5V 25° 65Msps LTC2272: AC Grounded Input Histogram 10000 9000 8000 7000 6000 5000 ...
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... LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. LTC2272: 64k Point FFT 14.01MHz and 15.8MHz, IN –15dBFS, PGA = 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) 22732 G35 LTC2272: 128k Point FFT 70MHz, –20dBFS, IN PGA = 0, Dither “ ...
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... SNR 100 2.8 22732 G47 360 5MHz 320 70MHz 280 240 1.25 1.50 1.75 2.00 22732 G49 LTC2273/LTC2272 V = 3.3V 1.5V 25° LTC2272: SNR vs Input Frequency 100 200 400 INPUT FREQUENCY (MHz) 22732 G45 LTC2272: SNR and SFDR vs Supply Voltage (V ...
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... LTC2273/LTC2272 TYPICAL PERFORMANCE CHARACTERISTICS otherwise noted. CMLOUT Dual-Dirac BER Bathtub Curve, 400Mbps 1.0E+00 1.0E–02 1.0E–04 1.0E–06 1.0E–08 1.0E – 10 1.0E–12 1.0E–14 0 0.2 0.4 UNIT INTERVAL (UI) CMLOUT Dual-Dirac BER Bathtub Curve, 1.6Gbps 1.0E+00 1.0E–02 1.0E–04 1.0E–06 1.0E–08 1.0E – 10 1.0E–12 1.0E–14 0 0.2 0.4 UNIT INTERVAL (UI) CMLOUT Eye Diagram 1.3Gbps 100mV/DIV 128 ...
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... D16.2) for establishing a negative running disparity for the fi rst data code-group after synchronization. LTC2273/LTC2272 SRR0 (Pin 17): Sample Rate Range Select Bit0. Used with the SRR1 pin to select the sample rate operating range. SRR1 (Pin 18): Sample Rate Range Select Bit1. Used with the SRR0 pin to select the sample rate operating range ...
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... LTC2273/LTC2272 PIN FUNCTIONS FAM (Pin 31): Frame Alignment Monitor Enable. A high level enables the substitution of predetermined data at the end of the frame with a K28.7 symbol for frame alignment monitoring. PAT0 (Pin 32): Pattern Select Bit0. Use with PAT1 to select a test pattern for the serial interface. ...
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... ENC PIPELINED ADC STAGES THIRD FOURTH FIFTH STAGE STAGE STAGE CORRECTION CONTROL LOGIC – ENC PGA DITH MSBINV SHDN Figure 1. Functional Block Diagram LTC2273/LTC2272 FAM 8B/10B ENCODER 16 20 LOGIC SERIALIZER 20X CLK SCRAMBLER/ PATTERN PLL GENERATOR PAT1 PAT0 SCRAM SRR1 SRR0 ...
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... LTC2273/LTC2272 DEFINITIONS DYNAMIC PERFORMANCE TERMS Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band lim- ited to frequencies above DC to below half the sampling frequency ...
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... K28.5 commas. An Idle Ordered Set is defi ned in the IEEE Std 802.3-2002 part3, Clause 36.2.4.12. In general K28.5 comma followed by either a D5 D16.2. If the running dispar- ity after the transmission of the K28.5 comma is positive, LTC2273/LTC2272 polynomial, 22732f ...
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... LTC2273/LTC2272 DEFINITIONS a D16.2 will be transmitted after the comma, otherwise a D5.6 will be transmitted. The result is that the ending disparity of an idle ordered set will always be negative. Initial Frame Synchronization The process of communicating frame synchroniza-tion information to the receiver upon the request of the receiver. For JESD204 compliance, K28.5 commas are transmitted as the preamble ...
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... The successive stages of the pipeline operate on alternating phases of the clock so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. LTC2273/LTC2272 The pipelined ADC of the LTC2273/LTC2272 has two phases of operation determined by the state of the differential + – ENC /ENC input pins ...
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... LTC2273/LTC2272 APPLICATIONS INFORMATION SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2273/ LTC2272 CMOS differential sample and hold. The differ- ential analog inputs are sampled directly onto sampling capacitors (C ) through NMOS transistors. The SAMPLE capacitors shown attached to each input (C the summation of all other capacitance associated with each input ...
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... The LTC2273/ LTC2272 do not require any input fi lter to achieve data sheet specifi cations; however, no fi ltering will put more stringent noise requirements on the input drive circuitry ...
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... Reference Operation Figure 6 shows the LTC2273/LTC2272 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifi er and control circuit. The LTC2273/LTC2272 have three modes of reference operation: Internal Refer- ence, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to V use an external reference, simply apply either a 1 ...
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... Figure 10. ENC Drive Using a CMOS to PECL Translator LTC2273/LTC2272 LTC2273/LTC2272 INTERNAL ADC CLOCK DRIVERS 1. 1. 22732 F08a Figure 8a. Equivalent Encode Input Circuit + ENC V = 1.6V THRESHOLD LTC2273/ – 1.6V ENC LTC2272 0.1μF 22732 F09 Figure 9. Single-Ended ENC Drive, Not Recommended for Low Jitter LTC2273/ LTC2272 22732 F10 22732f 25 ...
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... Internal Dither The LTC2273/LTC2272 are 16-bit ADC with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches ...
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... BIT BIT BIT BIT BIT BIT BIT ONE FRAME SERIAL OUT LTC2273/LTC2272 CMLOUT 8b10b SERIALIZER ENCODER CMLOUT MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR 22732 F11 DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF LSB BIT BIT BIT BIT ...
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... Upon detecting the deactivation of the synchronization request, the LTC2273/LTC2272 continue to transmit the synchronization preamble until the end of the frame. • At the start of the next frame, the LTC2273/LTC2272 will begin transmitting data characters. • The receiver designates the fi rst data character received after the preamble transmission to be the start of the frame. The fi ...
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... N – – Low Transition to Comma Output Timing (ISMODE is Low LAT SD K28.5 (x2) K28.5 (x2) + High Transition to Data Output Timing (ISMODE is Low) LTC2273/LTC2272 – 7 K28.5 (x2) K28.5 (x2 – – 6 22732 F14b 22732 F14a 22732f 29 ...
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... SCRAM pin to a high logic level. The polynomial used for 14 15 the scrambler which is a pseudo-random 15 pattern repeating itself every 2 –1. Figure 16 illustrates the LTC2273/LTC2272 implementation of this polynomial in parallel form. 30 START WAIT FOR NEXT FRAME CLOCK SYNC YES REQUEST? ...
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... APPLICATIONS INFORMATION SECOND OCTET FROM ADC D8 D9 D10 D11 FIRST OCTET D12 D13 D13 D15 MSB Figure 16. LTC2273/LTC2272 16-Bit LTC2273/LTC2272 SAMPLE_CLK SS0 SS1 SS2 SS3 SECOND SCRAMBLED OCTET C SS4 ...
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... LTC2273/LTC2272 APPLICATIONS INFORMATION FRAME_CLK SECOND SCRAMBLED OCTET FROM 8B/10B DECODER FIRST SCRAMBLED OCTET Figure 17. Required 16-Bit SS0 SS1 SS2 SS3 SS4 SS5 SS6 SS7 SF0 ...
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... Table 1. Frame Alignment Monitoring Modes FAM Mode 1 FAM Mode 2 FAM OFF previous frame, the LTC2273/LTC2272 will replace the second code group with the control character K28.7 before serialization. However K28.7 symbol was already transmitted in the previous frame, the actual code group will be transmitted. ...
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... LTC2273/LTC2272 APPLICATIONS INFORMATION START SCRAMBLE ADC DATA IF SCRAM IS ENABLED GENERATE 8B/10B CODE-GROUPS 1 AND FAM ENABLED? TRANSMIT CODE GROUP 1 TRANSMIT CODE GROUP 2 NO TRANSMIT CODE GROUP 2 22732 F18 PLL Operation The PLL has been designed to accommodate a wide range of sample rates. The SRR0 and SRR1 pins are used to confi ...
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... Heat Transfer Most of the heat generated by the LTC2273/LTC2272 are transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board critical that the exposed pad and all ground pins are connected to a ground plane of suffi ...
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... LTC2273/LTC2272 APPLICATIONS INFORMATION SERIAL CML DRIVER 50Ω + DATA – DATA GND Figure 19a. CML Termination, Directly-Coupled Mode (Preferred) SERIAL CML DRIVER 50Ω + DATA – DATA GND Figure 19b. CML Termination, Directly-Coupled Differential Mode 36 1. 50Ω 50Ω TRANSMISSION LINE + CMLOUT – ...
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... APPLICATIONS INFORMATION SERIAL CML DRIVER 50Ω + DATA – DATA 16mA GND 1.4V TO 3.3V VTERM OV DD 50Ω 50Ω 0.01μF TRANSMISSION LINE + CMLOUT 0.01μF – CMLOUT 50Ω TRANSMISSION LINE Figure 19c. CML Termination, AC-Coupled Mode LTC2273/LTC2272 SERIAL CML RECEIVER 50Ω 50Ω 22732 F19c 37 22732f ...
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... LTC2273/LTC2272 TYPICAL APPLICATIONS 38 Silkscreen Top Top Side 22732f ...
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... TYPICAL APPLICATIONS LTC2273/LTC2272 Inner Layer 2 Inner Layer 3 22732f 39 ...
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... LTC2273/LTC2272 TYPICAL APPLICATIONS 40 Inner Layer 4 Inner Layer 5 22732f ...
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... TYPICAL APPLICATIONS LTC2273/LTC2272 Bottom Side Silkscreen Bottom 22732f 41 ...
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... LTC2273/LTC2272 TYPICAL APPLICATIONS DD V SCRAM FAM P1 PDSER P2 PDADC P3 MSBINV P4 NC PGA P5 NC PAT1 P6 NC PAT0 DITH ISMODE P1 PLL0 P2 PLL1 P3 RX_ER GND 42 PBUS15 RXD15 PBUS14 RXD14 TXD15 GND GND PBUS13 RXD13 TXD14 PBUS12 RXD12 ...
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... Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 0.05 6.50 0.05 5.10 0.05 4.50 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 0.75 0. 0.10 TYP 4.50 REF (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2273/LTC2272 R = 0.115 TYP 39 40 0.40 0. PIN 1 NOTCH R = 0.45 OR 0.35 45 CHAMFER 4.42 0.10 4.42 0.10 (UJ40) QFN REV Ø 0406 0.25 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD ...
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... LTC2273/LTC2272 RELATED PARTS PART NUMBER DESCRIPTION LTC1993-2 High Speed Differential Op Amp LTC1994 Low Noise, Low Distortion Fully Differential Input/ Output Amplifi er/Driver LTC2215 16-Bit, 65Msps, Low Noise ADC LTC2216 16-Bit, 80Msps, Low Noise ADC LTC2217 16-Bit, 105Msps, Low Noise ADC LTC2202 16-Bit, 10Msps, 3 ...