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s29al008j

Manufacturer Part Number
s29al008j
Description
8 Megabit 1 M X 8-bit/512 K X 16-bit Cmos 3.0 Volt-only Boot Sector Flash Memory
Manufacturer
Meet Spansion Inc.
Datasheet

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S29AL008J
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
Data Sheet (Advance Information)
Notice to Readers: This document contains information on one or more products under development at
Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this
proposed product without notice.
Publication Number S29AL008J_00
Revision 04
Issue Date May 23, 2008
S29AL008J Cover Sheet

Related parts for s29al008j

s29al008j Summary of contents

Page 1

... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. Publication Number S29AL008J_00 Revision 04 Issue Date May 23, 2008 S29AL008J Cover Sheet ...

Page 2

... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S29AL008J S29AL008J_00_04 May 23, 2008 ...

Page 3

... Pinout and software compatible with single-power supply Flash – Superior inadvertent write protection Publication Number S29AL008J_00 This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. ...

Page 4

... General Description The S29AL008J Mbit, 3.0 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball Fine-pitch BGA (0.8 mm pitch), and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3 ...

Page 5

... Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Special Handling Instructions Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 S29AL008J Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7. Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 Requirements for Reading Array Data 7.3 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4 Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 ...

Page 6

... TSOP and BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 20. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 20.1 TS 048—48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 20.2 VBK048—48-Ball Fine-Pitch Ball Grid Array (BGA 21. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S29AL008J S29AL008J_00_04 May 23, 2008 ...

Page 7

... Toggle Bit Timings (During Embedded Algorithms Figure 17.10 DQ2 vs. DQ6 for Erase and Erase Suspend Operations Figure 17.11 Temporary Sector Unprotect/Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 17.12 Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 17.13 Alternate CE# Controlled Write Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 May 23, 2008 S29AL008J_00_04 ( S29AL008J 7 ...

Page 8

... S29AL008J Device Bus Operations Table 7.2 S29AL008J Top Boot Block Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7.3 Secured Silicon Sector Addresses (Top Boot Table 7.4 S29AL008J Bottom Boot Block Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 7.5 Secured Silicon Sector Addresses (Bottom Boot Table 7.6 S29AL008J Autoselect Codes (High Voltage Method Table 9.1 CFI Query Identification String Table 9 ...

Page 9

... V SS RESET# State WE# Control BYTE# WP# Command Register CE# OE# V Detector CC A0–A18 May 23, 2008 S29AL008J_00_04 ( Family Part Number Voltage Range 2.7–3 for full specifications. Sector Switches Erase Voltage Generator PGM Voltage ...

Page 10

... DQ11 35 DQ3 34 DQ10 33 DQ2 32 DQ9 31 DQ1 30 DQ8 29 DQ0 BYTE# DQ15/A DQ14 DQ13 DQ6 DQ12 V DQ4 DQ10 DQ11 DQ3 DQ8 DQ9 DQ1 CE# OE S29AL008J_00_04 May 23, 2008 ...

Page 11

... WP# RESET# RY/BY Logic Symbol May 23, 2008 S29AL008J_00_04 ( addresses 15 data inputs/outputs DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) Selects 8-bit or 16-bit mode Chip enable Output enable Write enable Write protect: The WP# contains an internal pull-up ...

Page 12

... Support) = 3.0-3.6V, bottom boot sector device (CFI Support) Package Type Description (Note 1) TS048 (Note 3) TSOP (Note 1) VBK048 (Note 4) Fine-Pitch BGA (Note 1) TS048 (Note 3) TSOP (Note 1) VBK048 (Note 4) Fine-Pitch BGA (Note 1) TS048 (Note 3) TSOP (Note 1) VBK048 (Note 4) Fine-Pitch BGA S29AL008J_00_04 May 23, 2008 ...

Page 13

... No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses May 23, 2008 S29AL008J_00_04 ( Table 7.1 S29AL008J Device Bus Operations Addresses CE# OE# WE# ...

Page 14

... Read Operations on page Characteristics CC1 , and OE Word/ Table 7.2 on page 16 has details on Autoselect Mode on page 18 read specifications apply. Refer to Write for timing diagrams. ± 0 but not within IH DC Characteristics S29AL008J_00_04 May 23, 2008 for and and AC ...

Page 15

... RESET# pin returns to V Refer to the tables in for the timing diagram. May 23, 2008 S29AL008J_00_04 ( ns. The automatic sleep mode is independent of the ACC represents the automatic sleep mode current specification ...

Page 16

... Address range is A18:A-1 in byte mode and A19:A0 in word mode. See Sector Size (bytes/words) 256/128 output from the device is disabled. The output pins are placed in the high IH Table 7.2 S29AL008J Top Boot Block Sector Addresses Sector Size A16 A15 A14 A13 A12 (Kbytes/ Kwords) ...

Page 17

... Address range is A18:A-1 in byte mode and A19:A0 in word mode. See the Sector Size (bytes/words) 256/128 May 23, 2008 S29AL008J_00_04 ( Table 7.4 S29AL008J Bottom Boot Block Sector Addresses Sector Size A16 A15 A14 A13 A12 ...

Page 18

... DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Definitions on page 26 Table 7.6 S29AL008J Autoselect Codes (High Voltage Method) Description Mode Manufacturer ID: Spansion Word ...

Page 19

... RESET# pin, all the previously protected sectors are protected again. Figure 17.11 on page 47 Notes 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. May 23, 2008 S29AL008J_00_04 ( shows the timing diagrams, for this feature. Figure 7.1 Temporary Sector Unprotect Operation ...

Page 20

... Read from sector address with Set up next sector No address Data = 00h? Yes No Last sector verified? Yes Remove V ID from RESET# Write reset command Sector Unprotect complete S29AL008J_00_04 May 23, 2008 ...

Page 21

... Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array. May 23, 2008 S29AL008J_00_04 ( Figure 7.2 on page ...

Page 22

... Write 40h to SecSi Sector address with Read from SecSi Sector address with S29AL008J unprotected. protected from RESET# Write reset command SecSi Sector Protect Verify complete S29AL008J_00_04 May 23, 2008 ...

Page 23

... May 23, 2008 S29AL008J_00_04 ( Table 9.1 Table 9.1 CFI Query Identification String Data 20h 0051h 22h 0052h Query Unique ASCII string “QRY” 24h ...

Page 24

... Not Supported Word Page Word Page ACC (Acceleration) Supply Minimum 9Ah 0000h 00 = Not Supported, D7-D4: Volt, D3-D0: 100mV ACC (Acceleration) Supply Maximum 9Ch 0000h 00 = Not Supported, D7-D4: Volt, D3-D0: 100mV S29AL008J Description N byte N Description S29AL008J_00_04 May 23, 2008 ...

Page 25

... Power-Up Write Inhibit If WE and OE edge of WE#. The internal state machine is automatically reset to reading array data on power-up. May 23, 2008 S29AL008J_00_04 ( Table 9.4 Primary Vendor-Specific Extended Query (Sheet Data WP# Protection 00 = Uniform Device without WP Protect ...

Page 26

... Figure 17.1 on page 40 Table 10.1 on page 31 on address bit A9. ID for valid sector addresses. S29AL008J Erase Suspend/ 26. Read Operations shows the timing diagram. shows the address and data Table 7.6 on page 18, which is intended for Table 7.2 on page 16 S29AL008J_00_04 May 23, 2008 AC and ...

Page 27

... The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Figure 10.1 on page 28 on page 43 for parameters, and to May 23, 2008 S29AL008J_00_04 ( for further information. Write Operation Status on page 32 illustrates the algorithm for the program operation ...

Page 28

... See Figure 17.6 on page 44 for timing diagrams. S29AL008J START Data Poll from System Verify Data? No Yes Yes Completed shows the address and data requirements Erase/Program Operations S29AL008J_00_04 May 23, 2008 Write ...

Page 29

... The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See information. May 23, 2008 S29AL008J_00_04 ( Write Operation Status on page 32 for information on these status bits ...

Page 30

... Figure 10.2 Erase Operation START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed for erase command sequence. for more information. S29AL008J Autoselect Command Sequence S29AL008J_00_04 May 23, 2008 ...

Page 31

... The Reset command is required to return to reading array data when device is in the autoselect mode DQ5 goes high (while the device is providing status data). May 23, 2008 S29AL008J_00_04 ( Table 10.1 S29AL008J Command Definitions Bus Cycles (Notes 2–5) First Second Third Addr ...

Page 32

... and the following subsections describe the functions of these bits. DQ7, Figure 17.8 on page 45, illustrates this. shows the outputs for Data# Polling on DQ7. S29AL008J Figure 11.2 on page 35 shows the Data# S29AL008J_00_04 May 23, 2008 ...

Page 33

... Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode the standby mode. Table 11.1 on page 36 on page 41, Figure 17.5 on page 44 and erase operations, respectively. May 23, 2008 S29AL008J_00_04 ( Figure 11.1 Data# Polling Algorithm START Read DQ7–DQ0 Addr = VA ...

Page 34

... S29AL008J Figure 11.2 on page 35 shows the toggle explains the algorithm. Figure 17.10 on page 46 shows the differences DQ2: Toggle Bit II on page 34. Table 11.1 on page 36 to compare Reading Toggle Bits subsection. Figure 17.10 on page 46 shows the differences S29AL008J_00_04 May 23, 2008 ...

Page 35

... Notes 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text. May 23, 2008 S29AL008J_00_04 ( for the following discussion. Whenever the system initially begins reading Figure 11 ...

Page 36

... Toggle 1 No toggle Data Data DQ7# Toggle for more information. S29AL008J Table 11.1 shows the outputs for DQ3. DQ5 DQ2 (Note 1) DQ3 (Note 2) RY/BY# 0 N/A No toggle 0 1 Toggle 0 N/A Toggle Data Data Data 0 N/A N/A DQ5: S29AL008J_00_04 May 23, 2008 ...

Page 37

... Ambient Temperature V Supply Voltages CC Note Operating ranges define those limits between which the functionality of the device is guaranteed. May 23, 2008 S29AL008J_00_04 ( (Note 2) (Note 3) 37. Maximum DC voltage on input or I/O pins is +2.0 V for periods ns. See Figure 13 ...

Page 38

... ±1.0 5 MHz MHz MHz MHz ± 0.3 V/-0.1V, 0 max 0.2 5 ± 0 0.2 5 0.1 0 8.5 12.5 0.45 CC min 0. min CC V –0.4 CC min CC 2.1 2 ns. ACC S29AL008J_00_04 May 23, 2008 Unit µ µA µA µA V ...

Page 39

... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 16. Key to Switching Waveforms Waveform V CC Input 0.0 V May 23, 2008 S29AL008J_00_04 ( Figure 15.1 Test Setup Device Under Test C L 6.2 kΩ ...

Page 40

... SR/W t OEH t CE HIGH Z S29AL008J Speed Options Test Setup 55 70 Min Max Max Max 30 30 Max 16 Max 16 Min 20 Min 0 Min 10 Min HIGH Z Output Valid S29AL008J_00_04 May 23, 2008 Unit ns ...

Page 41

... RESET# Low to Standby Mode RPD t RY/BY# Recovery Time RB Note Not 100% tested. RY/BY# CE#, OE# RESET# RY/BY# CE#, OE# RESET# May 23, 2008 S29AL008J_00_04 ( Description (See Note) (See Note) (See Note) Figure 17.2 RESET# Timings Ready Reset Timings NOT during Embedded Algorithms ...

Page 42

... The falling edge of the last WE# signal t SET ( and t specifications S29AL008J Speed Options 55 70 Max 5 Max 16 Min 55 70 Data Output (DQ0–DQ7) Address Input Data Output (DQ0–DQ14) DQ15 Output (t ) HOLD AH S29AL008J_00_04 May 23, 2008 Unit ns ...

Page 43

... BUSY t CEH Notes 1. Not 100% tested. 2. See Erase and Programming Performance on page 49 May 23, 2008 S29AL008J_00_04 ( Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# Low During Toggle Bit Polling ...

Page 44

... 55h 30h 10 for Chip Erase S29AL008J Read Status Data (last two cycles WHWH1 Status D OUT t RB Read Status Data WHWH2 In Complete Progress t t BUSY RB Write Operation Status on page 32). S29AL008J_00_04 May 23, 2008 ...

Page 45

... DQ0–DQ6 t BUSY RY/BY# Note VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. May 23, 2008 S29AL008J_00_04 ( Figure 17.7 Back to Back Read/Write Cycle Timing t t ...

Page 46

... BUSY Erase Enter Erase Suspend Suspend Program Erase Erase Suspend Erase Suspend Read Program S29AL008J Valid Status Valid Data (stops toggling) Erase Resume Erase Erase Erase Suspend Complete Read S29AL008J_00_04 May 23, 2008 ...

Page 47

... SA, A6, A1, A0 Data CE# WE# OE# Note For sector protect For sector unprotect May 23, 2008 S29AL008J_00_04 ( Description V Rise and Fall Time (See Note) ID RESET# Setup Time for Temporary Sector Unprotect ...

Page 48

... Min 55 70 Min 0 Min 45 Min 45 45 Min 0 Min 0 Min 0 Min 0 Min 0 Min 35 35 Min 25 Min 20 Byte Typ 6 Word Typ 6 Typ 0.5 Data# Polling PA DQ7# D OUT = data written to the device. OUT S29AL008J_00_04 May 23, 2008 Unit µs sec ...

Page 49

... The device has a minimum erase and program cycle endurance of 100,000 cycles per sector. 19. TSOP and BGA Pin Capacitance Parameter Symbol OUT C IN2 Notes 1. Sampled, not 100% tested. 2. Test conditions T = 25° 1.0 MHz. A May 23, 2008 S29AL008J_00_04 ( Typ (Note 1) Max (Note 2) 0 150 ° ...

Page 50

... (N/2 TIPS) 0.10 REVERSE PIN OUT (TOP VIEW SEATING PLANE 0.08MM (0.0031" WITH PLATING ( BASE METAL SECTION B-B e DETAIL B S29AL008J_00_04 May 23, 2008 3355 \ 16-038.10c ...

Page 51

... SYMBOL MIN A --- A1 0.18 A2 0.62 D 8.15 BSC. E 6.15 BSC. D1 5.60 BSC. E1 4.00 BSC φb 0.35 e 0.80 BSC 0.40 BSC. May 23, 2008 S29AL008J_00_04 ( 0.10 (4X TOP VIEW 0.10 A2 SEATING PLANE 0.08 C SIDE VIEW NOTES: N/A NOM MAX NOTE --- 1.00 OVERALL THICKNESS --- ...

Page 52

... Added the Extended Temperature Range Ordering Information Updated the Valid Combination table Updated Pin Configuration table Pin Configuration Updated the S29AL008J Device Bus Operation table and modified Note 3 Device Bus Operation Added Extended Temperature Range information Operating Ranges Added Regulated Voltage ...

Page 53

... ORNAND2 , HD-SIM and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. May 23, 2008 S29AL008J_00_04 ( ® , the Spansion Logo, MirrorBit S29AL008J ® ...

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