ad7868bq Analog Devices, Inc., ad7868bq Datasheet - Page 4

• Manufacturer Part Number: ad7868bq
• Description: Lc2mos Complete, 12-bit Analog I/o System
• Manufacturer: Analog Devices, Inc.

TIMING CHARACTERISTICS
AD7868
Parameter
ADC TIMING
DAC TIMING
NOTES
1
2
3
4
5
6
ABSOLUTE MAXIMUM RATINGS*
(T
V
V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
V
V
RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to V
RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V
RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V
Digital Inputs to AGND . . . . . . . . . . . –0.3 V to V
Digital Outputs to AGND . . . . . . . . . . –0.3 V to V
Operating Temperature Range
Storage Temperature Range . . . . . . . . . . . . –65 C to +150 C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300 C
Power Dissipation (Any Package) to +75 C . . . . . . . . 450 mW
Derates above +75 C by . . . . . . . . . . . . . . . . . . . . 10 mW/ C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7868 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Timing specifications are sample tested at +25 C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
Serial timing is measured with a 4.7 k pull-up resistor on DR and RFS and a 2 k pull-up resistor on RCLK . The capacitance on all three output is 35 pF.
When using internal clock, RCLK mark/space ratio (measured from a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space ratio =
DR will drive higher capacitance loads but this will add to t
Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.
TCLK mark/space ratio is 40/60 to 60/40.
voltage level of 1.6 V.
external clock mark/space ratio.
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
t
t
t
t
t
t
t
t
t
t
t
t
t
DD
SS
OUT
IN
1
2
3
4
5
6
13
7
8
9
10
11
12
A
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40 C to +85 C
T Version . . . . . . . . . . . . . . . . . . . . . . . . . –55 C to +125 C
3
4
6
= +25 C unless otherwise noted)
5
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
to AGND . . . . . . . . . . . . . . . . V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Limit at T
(A, B Versions)
50
440
100
20
100
155
4
100
2 RCLK +200 to
3 RCLK + 200
50
75
150
30
75
40
MIN
SS
, T
1, 2
–0.3 V to V
MAX
(V
DD
5
= +5 V
since it increases the external RC time constant (4.7 k /C
440
155
3 RCLK + 200
200
Limit at T
(T Version)
50
100
20
100
4
100
2 RCLK +200 to
50
100
40
100
40
DD
DD
DD
DD
DD
DD
DD
SS
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+0.3 V
to V
5%, V
DD
MIN
SS
–4–
, T
= –5 V
MAX
CONVST
RO DAC
RI DAC
DGND
AGND
RCLK
V
CLK
RFS
V
OUT
V
DR
DD
SS
5%, AGND = DGND = 0 V)
Units
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns typ
ns min
ns min
ns min
ns min
ns min
ns min
10
11
12
1
2
3
4
5
6
7
8
9
NC = NO CONNECT
(Not to Scale)
AD7868
TOP VIEW
DIP
Conditions/Comments
CONVST Pulse Width
RCLK Cycle Time, Internal Clock
RFS to RCLK Falling Edge Setup Time
RCLK Rising Edge to RFS
RCLK to Valid Data Delay, C
Bus Relinquish Time after RCLK
CONVST to RFS Delay
TFS to TCLK Falling Edge
TCLK Falling Edge to TFS
TCLK Cycle Time
Data Valid to TCLK Setup Time
Data Valid to TCLK Hold Time
LDAC Pulse Width
PIN CONFIGURATIONS
24
23
22
21
20
19
18
17
16
15
14
13
CONTROL
V
V
V
RO ADC
AGND
NC
DGND
TCLK
DT
TFS
LDAC
DD
SS
IN
L
) and hence the time to reach 2.4 V.
WARNING!
CONVST
RO DAC
RI DAC
DGND
AGND
RCLK
V
CLK
RFS
V
OUT
V
NC
DR
NC
DD
SS
10
11
12
13
14
1
2
3
4
5
6
7
8
9
NC = NO CONNECT
(Not to Scale)
ESD SENSITIVE DEVICE
AD7868
TOP VIEW
SOIC
L
= 35 pF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REV. B
V
V
NC
V
NC
NC
TFS
LDAC
CONTROL
RO ADC
AGND
DGND
TCLK
DT
SS
DD
IN