ics950410 Integrated Device Technology, ics950410 Datasheet
ics950410
Available stocks
Related parts for ics950410
ics950410 Summary of contents
Page 1
... This Output has 2X Default Drive and can be programmaed lower via IIC HTT PCI MHz MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 33.40 30.00 30.00 35.00 30.00 33.75 33.33 33.33 37.50 ICS950410 Preliminary Product Preview Pin Configuration 48 REF1/FS1* 47 GND VDDREF Reset# GND 5 44 VDDA 43 GND 42 CPUCLK8T0 41 CPUCLK8C0 40 VDDCPU GND 10 39 CPUCLK8T1 38 CPUCLK8C1 37 GND 36 VDDCPU 35 CPUCLK8T2 ...
Page 2
... ICS950410 Preliminary Product Preview Pin Descriptions PIN PIN # PIN NAME TYPE 1 I/O ~*FS0/REF0 2 VDDHTT PWR OUT 5 GND PWR 6 *ModeA/HTTCLK0 I/O 7 *ModeB/PCICLK8/HTTCLK1 I/O 8 PCICLK9/HTTCLK2 OUT 9 VDDPCI PWR 10 GND PWR 11 PCICLK11/HTTCLK3 OUT 12 *FS2/PCICLK10 I/O 13 PCICLK0 OUT 14 PCICLK1 OUT 15 GND PWR 16 VDDPCI PWR 17 PCICLK2 OUT 18 PCICLK3 ...
Page 3
... Clawhammer and Sledgehammer with AMD, VIA or ALI systems. The ICS950410 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the ...
Page 4
... ICS950410 Preliminary Product Preview Table1: Frequency Selection Table Bit4 Bit3 Bit2 Bit1 Bit0 CPU FS4 FS3 FS2 FS1 FS0 MHz 100. 133. 168. 202. 100. 133. 166.70 ...
Page 5
... Index Block Read Operation Controller (Host) T Slave Address D2 WR ACK Beginning Byte = N ACK RT ACK Slave Address D3 RD ACK ACK ICS950410 . ICS (Slave/Receiver) starT bit (H) WRite ACK ACK Repeat starT (H) ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK Byte ...
Page 6
... ICS950410 Preliminary Product Preview Table: Frequency Select Register Byte 0 Pin # - SS_EN Bit 7 - SEL24_48MHz Bit Source Select Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit Table: Output Control Register Byte 1 Pin # 1 CPUCLK8T/C2 Bit 7 6 HTTCLK0 Bit 6 7 PCICLK8/HTTCLK1 Bit 5 8 PCICLK9/HTTCLK2 ...
Page 7
... Control Function Type BC7 BC6 BC5 Byte Count BC4 Programming b(7:0) BC3 BC2 BC1 BC0 Name Control Function Type Revision ID Vendor ID 7 ICS950410 Preliminary Product Preview 00: 0.5X Drive 10: 1.5X Drive RW 01: 1.0X Drive 11: 2.0X Drive RW 00: 0.5X Drive 10: 1.5X Drive RW 01: 1.0X Drive 11: 2.0X Drive RW 00: 0.5X Drive 10: 1.5X Drive RW 01: 1 ...
Page 8
... ICS950410 Preliminary Product Preview Table: Skew Control Register Byte 8 Pin # - PCI/HTTSkw3 Bit 7 - PCI/HTTSkw2 Bit 6 - PCI/HTTSkw1 Bit 5 - PCI/HTTSkw0 Bit 4 - PCISkw3 Bit 3 - PCISkw2 Bit 2 - PCISkw1 Bit 1 - Bit 0 PCISkw0 Table: WD Time Control & Async Frequency Selection Register Byte 9 Pin # - Bit 7 - Bit 6 - REF1 Strength ...
Page 9
... Spread Spectrum RW Programming b(14:8) RW SSP9 RW SSP8 RW 9 ICS950410 Preliminary Product Preview 0 1 The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+ These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage ...
Page 10
... ICS950410 Preliminary Product Preview Absolute Maximum Rating PARAMETER SYMBOL 3.3V Core Supply Voltage VDD_A 3.3V Logic Input Supply VDD_In Voltage Storage Temperature Ts Ambient Operating Temp Tambient Case Temperature Tcase Input ESD protection HBM ESD prot 1 Guaranteed by design and characterization, not 100% tested in production. ...
Page 11
... USB48 Rising/Falling edge rate 0 2 0 ICS950410 NOTES TYP MAX UNITS Ω 250 ps ...
Page 12
... ICS950410 Preliminary Product Preview Electrical Characteristics - CPUCLKK8T/C K8 3.3V Push Pull Differential Pair PARAMETER SYMBOL δ V /δ t Rising Edge Rate δ V /δ t Falling Edge Rate Differential Voltage V DIFF ∆ V Change in V Magnitude DIFF_DC DIFF Common Mode Voltage V CM Change in Common Mode ∆ ...
Page 13
... OH V @MIN = 1. @MAX = 0 Rising/Falling edge rate ICS950410 TYP MAX UNITS Notes 300 ppm 1,2 69.8550 500 ps ...
Page 14
... ICS950410 Preliminary Product Preview Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS950410 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power- ...
Page 15
... Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 15 ICS950410 Preliminary Product Preview In Millimeters In Inches COMMON DIMENSIONS MIN MAX MIN 2.41 2.80 .095 ...
Page 16
... ICS950410 Preliminary Product Preview Revision History Rev. Issue Date Description 1. Updated Byte 11/12 M/N programming description 2. Updated Ordering Information from "Lead Free" to Annealed Lead Free". A 4/22/2005 3. Preliminary Release. 0888A—04/22/05 16 Page # 8-9,15 ...