ics951403 Integrated Device Technology, ics951403 Datasheet - Page 12

• Manufacturer Part Number: ics951403
• Description: Amd-k7 System Clock Chip
• Manufacturer: Integrated Device Technology

Notes:
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0486B—02/23/04
ICS951403
The ICS clock generator is a slave/receiver, I
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
Programmable System Frequency Generator
Brief I
Functionality &
Frequency Select
Register
Output Control Registers
Vendor ID & Revision ID
Registers
Byte Count
Read Back Register
Watchdog Timer
Count Register
Watchdog Control
Registers
VCO Control Selection
Bit
VCO Frequency Control
Registers
Spread Spectrum
Control Registers
Group Skews Control
Registers
Output Rise/Fall Time
Select Registers
Register Name
2
C registers description for ICS951403
2
C interface, the protocol is set to use only Block-Writes from the
10 Bit [6:0]
10 Bit [7]
11-12
13-14
15-16
17-20
Byte
1-6
0
7
8
9
Output frequency, hardware / I
frequency select, spread spectrum &
output enable control register.
Active / inactive output control
registers/latch inputs read back.
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00
this byte.
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
These registers control the spread
percentage amount.
Increment or decrement the group
skew amount as compared to the
initial skew.
These registers will control the
output rise and fall time.
2
C component. It can read back the data stored in the latches
12
Description
H
2
C
to
PWD Default
See individual
byte
description
See individual
byte
description
See individual
byte
description
Depended on
hardware/byte
0 configuration
Depended on
hardware/byte
0 configuration
See individual
byte
description
See individual
byte
description
000,0000
08
10
0
H
H