ics9248-168 Integrated Device Technology, ics9248-168 Datasheet

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ics9248-168

Manufacturer Part Number
ics9248-168
Description
Amd - K7?? Clock Generator For Mobile System
Manufacturer
Integrated Device Technology
Datasheet
AMD - K7™ Clock Generator for Mobile System
Third party brands and names are the property of their respective owners.
Recommended Application:
VIA KT133 style chipset
Output Features:
Features:
Block Diagram
SDRAM_STOP#
9248-168 Rev B 01/09/01
CPU_STOP#
BUFFER_IN
PCI_STOP#
SEL24_48#
1 - Differential pair open drain CPU clocks
1 - CPU clock @ 3.3V
7 - SDRAM @ 3.3V
8 - PCI @ 3.3V,
1 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz.
Up to 153MHz frequency support
Support power management: CPU stop and Power down
Mode from I
Spread spectrum for EMI control
(± 0.25% to ± 0.6% center, or 0 to -0.5% or -1.0% down
spread).
Uses external 14.318MHz crystal
FS (2:0)
SDATA
SCLK
PD#
X2
X1
2
XTAL
OSC
Integrated
Circuit
Systems, Inc.
C programming.
Spectrum
PLL2
Spread
Control
Config.
PLL1
Logic
Reg.
DIVDER
DIVDER
DRIVER
SDRAM
CPU
PCI
/ 2
Stop
Stop
Stop
48MHz
24_48MHz
CPUCLK
CPUCLKC0
CPUCLKT0
PCICLK (6:0)
PCICLK_F
SDRAM (5:0)
SDRAM_F
REF (2:0)
Functionality
*SEL24_48#/24_48MHz
F
0
0
0
0
S
1
1
1
1
* Internal Pull-up Resistor of 120K to VDD
1
2
2
*SDRAM_STOP#
*FS2/PCICLK_F
These outputs have double strength to drive 2 loads.
These outputs can be set to 1.5X strength through I
*FS1/PCICLK0
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
F
*PCI_STOP#
*FS0/48MHZ
BUFFER_IN
S
0
0
0
0
1
1
1
1
1
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDDREF
VDDPCI
VDDPCI
VDD48
AVDD
GND
GND
GND
GND
F
S
0
0
0
0
1
1
1
1
X1
X2
0
48-Pin 300mil SSOP
Pin Configuration
1
1
1
1
1
1
1
9
C
0
3
0
3
0
3
2
0
P
0
3
0
3
0
3
0
0 .
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0 .
3 .
0 .
3 .
0 .
3 .
0 .
U
1
2
3
4
5
6
7
8
9
0
0
3
0
3
0
3
0
3
3
3
3
3
3
3
3
P
3
3
3
3
3
0
0
. 3
C
3 .
3 .
3 .
3 .
3 .
0 .
0 .
3 3
ICS9248-168
I
3
3
3
3
3
0
0
0
0
+
+
+
+
+
+
S
- /
- /
o t
o t
- /
- /
- /
- /
p
. 0
. 0
. 0
. 0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
-
-
r
0
0
a e
5 3
5 3
0
0
6 .
6 .
5 2
5 2
5 .
5 .
%
%
%
%
%
%
d
%
%
C
C
P
C
C
C
C
D
D
e
e
r e
e
e
e
e
REF0
REF
REF2
GND
GND
VDD
CPUCLK
CPUCLKT0
CPUCLKC0
CPU_STOP#*
PD#*
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
t n
t n
o
o
t n
t n
t n
t n
e c
w
w
r e
r e
r e
r e
r e
r e
n
n
n
1
S
S
S
S
S
S
S
S
a t
1
p
p
p
p
p
p
p
p
e r
e r
e g
e r
e r
e r
e r
e r
e r
2
d a
d a
d a
d a
d a
d a
d a
d a
2
2
2
C

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ics9248-168 Summary of contents

Page 1

... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-168 Pin Configuration 48 1 ...

Page 2

... ICS9248-168 Pin Descriptions ...

Page 3

... General Description The ICS9248-168 is a main clock synthesizer chip for AMD-K7 based note book systems with VIA style chipset. This provides all clocks required for such a system. Spread spectrum may be enabled through I This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-168 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...

Page 4

... ICS9248-168 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ...

Page 5

... Note: Don’t write into this register, writing into this register can cause malfunction 5 ICS9248-168 ...

Page 6

... ICS9248-168 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...

Page 7

... Note 2 Note 2 Note required for switching, where ICS9248-168 MIN TYP MAX 1 1.8 0 0.9 1.6 0.8 1.6 45 51.5 55 200 125 300 250 MIN TYP MAX 60 1 1.8 0.8 18 0.5 0.9 0.3 0.9 0.4 Vpull-up(ext) + 0.6 0.2 Vpull-up(ext) + 0.6 1 ...

Page 8

... ICS9248-168 Electrical Characteristics - SDRAM_OUT 70C; V =3.3V +/-5 (unless otherwise specified PARAMETER SYMBOL 1 Output Impedance R DSP3 1 Output Impedance R DSN3 Output High Voltage V OH3 Output Low Voltage V OL3 I Output High Current OH3 I Output Low Current OL3 1 Rise Time Fall Time ...

Page 9

... V =V *( MHz 1 ICS9248-168 MIN TYP MAX UNITS 2.6 V 0 1.4 2.0 ns 1 280 400 ps 200 ps MIN TYP MAX UNITS ...

Page 10

... ICS9248-168 General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ...

Page 11

... If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area more important to locate the series termination resistor close to the driver than the programming resistor. Fig ICS9248-168 ...

Page 12

... Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-168 device shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. ...

Page 13

... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-168. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...

Page 14

... ICS9248-168 Ordering Information ICS9248yF-168-T Example: ICS XXXX PPP - T Third party brands and names are the property of their respective owners. SYMBOL VARIATIONS Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) ...

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