ics409 Integrated Device Technology, ics409 Datasheet - Page 3

• Manufacturer Part Number: ics409
• Description: Pc Peripheral Clock
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ PC PERIPHERAL CLOCK
ICS409
PC PERIPHERAL CLOCK
in pF. Example: For a crystal with a 15 pF load
capacitance, each crystal capacitor would be 18 pF
[(15-6) x 2] = 18.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the VDD
pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
Absolute Maximum Ratings
Recommended Operation Conditions
Stresses above the ratings listed below can cause permanent damage to the ICS409. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Item
3
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS409. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Selection of 40M/80M Clock
The 40/80M output clock is selected by a soft pull-up or
pull-down on 40/80M pin (pin 5). A rising edge on
OE/LAT latches in the high or low level on pin 5 which
starts the appropriate frequency.
+3.00
Min.
0
7 V
-0.5 V to VDD+0.5 V
0 to +70 ° C
-65 to +150 ° C
175 ° C
260 ° C
Typ.
–
Rating
+3.60
Max.
+70
ICS409
CLOCK SYNTHESIZER
Units
° C
REV D 092109
V