mpc9351 Integrated Device Technology, mpc9351 Datasheet - Page 6

• Manufacturer Part Number: mpc9351
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Integrated Device Technology

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9351
Low Voltage PLL Clock Driver
6
Programming the MPC9351
several divider modes; in addition, the external feedback of
the device allows for flexibility in establishing various input to
output frequency relationships. The output divider of the four
output groups allows the user to configure the outputs into
1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensures that the output duty cycle is always 50%.
Table 9
table describes the outputs using the input clock frequency
CLK as a reference.
Table 9. Output Frequency Relationship
Using the MPC9351 in Zero-Delay Applications
MPC9351. For these applications, the MPC9351 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Freescale MC100EP111 or
MC10EP222, taking advantage of its superior low-skew
performance. Clock trees using LVPECL for clock
distribution, and the MPC9351 as LVCMOS PLL fanout buffer
with zero insertion delay, will show significantly lower clock
skew than clock distributions developed from CMOS fanout
buffers.
for its use as a zero-delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
MPC9351 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t
(t
MPC9351
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB. More frequency ratios are
JIT(∅)
The MPC9351 clock driver outputs can be configured into
Nested clock trees are typical applications for the
The external feedback option of the MPC9351 PLL allows
The remaining insertion delay (skew error) of the
available by the connection of QA to the feedback input (EXT_FB).
FSELA
, phase or long-term jitter), feedback path delay and
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
illustrates the various output configurations. The
FSELB
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Inputs
FSELC
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
(1)
(∅)
APPLICATIONS INFORMATION
for an Example Configuration
), I/O jitter
FSELD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
6
relationship. In addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 25 MHz to
200 MHz, while the VCO frequency range is specified from
200 MHz to 400 MHz and should not be exceeded for stable
operation.
the output-to-output skew (t
output.
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
2 * CLK
2 * CLK
The output division settings establish the output
CLK
CLK
CLK
CLK
QA
fref = 100 MHz
Figure 3. . MPC9351 Zero-Delay Configuration
1
1
1
0
0
0
CLK ÷ 2
CLK ÷ 2
CLK ÷ 2
CLK ÷ 2
2 * CLK
2 * CLK
2 * CLK
2 * CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
QB
TCLK
REF_SEL
PLL_EN
FSELA
FSELB
FSELC
FSELD
Ext_FB
(Feedback of QD4)
100 MHz (Feedback)
Outputs
MPC9351
SK(O)
Advanced Clock Drivers Devices
relative to the feedback
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Freescale Semiconductor
QC
QC0
QC1
QD0
QD1
QD2
QD3
QD4
QA
QB
CLK ÷ 2
CLK ÷ 2
CLK ÷ 2
CLK ÷ 2
2 * CLK
2 * CLK
2 * CLK
2* CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
2 x 100 MHz
2 x 100 MHz
4 x 100 MHz
QD
NETCOM
MPC9351