mpc93h51 Integrated Device Technology, mpc93h51 Datasheet - Page 10

• Manufacturer Part Number: mpc93h51
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Integrated Device Technology

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC93H51
Low Voltage PLL Clock Driver
Figure 12. Propagation Delay (t
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MPC93H51
The variation in cycle time of a signal between adjacent cycles, over a random
sample of adjacent cycle pairs
Ext_FB
PCLK
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
PCLK
(PCLK)
Ext_FB
The deviation in t
in a random sample of cycles
TCLK
Figure 14. Output Duty Cycle (DC)
Figure 16. Cycle-to-Cycle Jitter
T
N
t
P
0
for a controlled edge with respect to a t
Figure 18. I/O Jitter
t
(∅)
Test Reference
T
N+1
T
0
DC = t
V
P
CMR
/T
PD
0
T
T
x 100%
JIT(CC)
JIT(∅)
, status phase offset)
= |T
= |T
N
0
-T
-T
1
N+1
mean|
V
V
GND
0
CC
CC
|
mean
÷2
V
V
GND
V
CC
CC
CMR
÷2
10
The pin-to-pin skew is defined as the worst case difference in propagation delay
between any similar delay path within a single device
Figure 13. Propagation Delay (t
Ext_FB
The deviation in cycle time of a signal with respect to the ideal period
over a random sample of cycles
TCLK
Figure 19. Transition Time Test Reference
Figure 15. Output-to-Output Skew t
t
F
T
0
Figure 17. Period Jitter
t
(∅)
Advanced Clock Drivers Device Data
t
SK(O)
Freescale Semiconductor
T
JIT(P)
PD
t
R
) Test Reference
= |T
V
CC
N
0.55
-1/f
2.4
= 3.3 V
SK(O)
0
|
V
V
GND
V
V
GND
V
V
GND
V
V
GND
CC
CC
CC
CC
CC
CC
CC
CC
÷2
÷2
÷2
÷2
NETCOM
MPC93H51