mpc9952 Freescale Semiconductor, Inc, mpc9952 Datasheet - Page 4

• Manufacturer Part Number: mpc9952
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Freescale Semiconductor, Inc

MPC9952
4. Termination of 50 to V CCO /2.
5. t pd is specified for 50MHz input ref, the window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods.
6. The PLL may be unstable with a divide by 2 feedback ratio.
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of approximately 7 the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091.
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
AC CHARACTERISTICS (T A = 0 to 70 C, V CC = 3.3V 5%)
MOTOROLA
t r , t f
t pw
t os
f VCO
f max
t pd
t PLZ , t PHZ
t PZL , t PLH
t jit(cc)
t lock
IN
IN
The MPC9952 clock driver was designed to drive high
In most high performance clock networks point–to–point
The t pd does not include jitter.
Symbol
Figure 3. Single versus Dual Transmission Lines
MPC9952
MPC9952
OUTPUT
OUTPUT
BUFFER
BUFFER
7
7
Output Rise/Fall Time (Note 4.)
Output Pulse Width (Note 4.)
Output-to-Output Skew
(Note 4.)
PLL VCO Lock Range
Maximum Output Frequency
REFCLK to FBIN Delay
Output Disable Time
Output Enable Time
Cycle–to–Cycle Jitter
Maximum PLL Lock Time
R S = 43
R S = 43
R S = 43
Characteristic
Z O = 50
Z O = 50
Z O = 50
Qa,Qb,Qc ( 4)
Excluding Qa0
APPLICATIONS INFORMATION
Qc,Qb ( 2)
All Outputs
All Outputs
Qa ( 6)
OutA
OutB0
OutB1
t CYCLE /2
–750
–200
0.10
4
Min
200
180
120
80
2
2
technique terminates the signal at the end of the line with a
50 resistance to V CCO /2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC9952 clock driver. For
the series terminated case however there is no DC current
draw, thus the outputs can drive multiple series terminated
lines. Figure 3 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC9952 clock
driver is effectively doubled due to its capability to drive
multiple lines.
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC9952 output buffers is
more than sufficient to drive 50
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC9952. The output
waveform in Figure 4 shows a step in the waveform, this step
is caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 43
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
The waveform plots of Figure 4 show the simulation
At the load end the voltage will double, due to the near
VL = VS (Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
t CYCLE /2
Typ
500
100
0
t CYCLE /2
+750
Max
350
450
550
480
200
1.0
10
10
8
Unit
MHz
MHz
ms
ns
ps
ps
ps
ns
ns
ps
transmission lines on the
0.8 to 2.0V
Same Frequencies
Same Frequencies
Different Frequencies
Note 6.
Note 4.
Notes 4., 5.
Note 4.
Note 4.
TIMING SOLUTIONS
Condition
DL207 — Rev 0
series resistor