lmx2322 National Semiconductor Corporation, lmx2322 Datasheet - Page 8

• Manufacturer Part Number: lmx2322
• Description: Pllatinumtm 2.0 Ghz Frequency Synthesizer For Rf Personal Communications
• Manufacturer: National Semiconductor Corporation

N register
R register
LMX2322
2.0 Programming Description
2.1
MSB
2.1.1
2.1.2
2.2
Rev 1.6
17
R REGISTER
MICROWIRE
The MICROWIRE
register consists of a 17 bit DATA field and a 1 bit address (ADDR) field as shown below. When Latch Enable
transitions HIGH, data stored in the shift register is loaded into either the R or N register depending on the ADDR
bit as described in Table 2.1.1. The data is loaded MSB first. The DATA field assignment for the R and N
registers are shown in Table 2.1.2 below.
If the Address Bit (ADDR) is 1, when LE is transitioned high data is transferred from the 18-bit shift register into
the 14-bit R register. The R register contains a latch which sets the PLL 10-bit R counter divide ratio. The divide
ratio is programmed using the bits R_CNTR as shown in Table 2.2.1. The ratio must be t 2. The PD_POL,
CP_TRI and TEST bits control the phase detector polarity, charge pump tri-state, and test mode respectively, as
shown in Table 2.2.2 . The RS bit is reserved and should always be set to zero. X denotes a don’t care condition.
Address bit Truth Table
When LE is transitioned high, data is transferred from the 18-bit shift register into either the 14-bit R register, or
the 17 bit N register depending upon the state of the ADDR bit.
Register Content Truth Table
17 16 15
17 16 15
First Bit
First Bit
X
X
DATA [16:0]
ADDR
0
1
X
X
X
X
TM
N register
R register
TM
DATA Location
Interface
TEST RS PD_POL CP_TRI
TEST RS PD_POL CP_TRI
interface is comprised of an 18 bit shift register, a R register and a N register. The shift
14
14
1
13
13
NB_CNTR
ADDR
SHIFT REGISTER BIT LOCATION
SHIFT REGISTER BIT LOCATION
0
12
12
LSB
9/24/1998
11
11
10 9 8 7 6 5 4 3
10 9 8 7 6 5 4 3
NA_CNTR
R_CNTR[9:0]
Advance Information
R_CNTR
CTL_WORD
2
2
Last Bit
Last Bit
1
1
0
0
1
0
1
8