vsc8113 Vitesse Semiconductor Corp, vsc8113 Datasheet
vsc8113
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vsc8113 Summary of contents
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... Equipment Loopback function which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel data bus and clock outputs.The VSC8113 also provides the option of selecting between either its internal CRU’s recovered clock and data signals or optics containing a G52154-0, Rev 4 ...
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... ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery CRU clock and data signals. (In this mode the VSC8113 operates just like the VSC8111). The receive section also contains a SONET/SDH frame detector circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel converter ...
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... The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8113 will con- tinually perform frame detection and recovery as long as this pin is held high even more frames has been detected ...
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... This LOS detection feature can be disabled by applying a high level to LOSDETEN_ input. The VSC8113 also has a TTL input LOSTTL and a PECL input LOSPECL to force the part into a Loss of Signal state. Most optics have a PECL output usu- ally called “ ...
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... Data Sheet VSC8113 RXDATAIN CRU Recovered Clock RXCLKIN TXDATAOUT TXCLKOUT FACLOOP Equipment Loopback The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral- lel to serial conversion of the low speed data (TXIN[7:0]) is selected and converted back to parallel data in the receiver section and presented at the low speed parallel outputs (RXOUT[7:0]) ...
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... Clock Synthesis The VSC8113 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector (PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed- back system ...
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... Note: Vitesse recommends a ( filter) C-L-C choke over using a ferrite bead. All ground planes should be tied together using multiple vias. The VSC8113 features a lock detect function for the CMU, called “CMULOCKDET”. It generates low going pulses when the CMU is locked to the incoming REFCLK. This is accomplished by comparing the phase of the synthesized clock to the reference clock. If the “ ...
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... CMU’s output frequency. Page 8 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Figure 6: External Integrator Capacitor CP = 0.1 F CP2 CP1 + - CN1 CN2 CN = 0.1 F VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 G52154-0, Rev 4.2 3/19/99 ...
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... The CRU is designed to tolerate this jitter with margin over the specification limits, see Figure 7. The CRU obtains and maintains lock based on the data transition information. When there is no transition on the data stream, the recovered clock frequency can drift. The VSC8113 can maintain lock over 100 bits of no switching on data stream. ...
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... TXIN [7:0] Page 10 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION T RXCLK T T RXSU RXH Description Description T PROP T CLKIN T INSU VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 Min Typ Max Units - 1.608 - ns 250 - - ps 250 - - ps Min Typ Max Units - 6 ...
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... Data Sheet VSC8113 Table 4: Transmit Data Input Timing Table (STS-12 Operation) Parameter T Transmit data input byte clock period CLKIN T Transmit data setup time with respect to TXLSCKIN INSU T Transmit data hold time with respect to TXLSCKIN INH Maximum allowable propagation delay for connecting ...
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... Skew between the falling edge of TXCLKOUT+ and T SKEW valid data on TXDATAOUT Page 12 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Description T TXCLK T T SKEW SKEW Description Description VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 Min Typ Max Units - 6. 51. 51.44 ...
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... Data Sheet VSC8113 Data Latency The VSC8113 contains several operating modes, each of which exercise different logic paths through the part. Table 10 bounds the data latency through each path with an associated clock signal. Table 10: Data Latency Circuit Mode Transmit Data TXIN [7:0] to MSB at TXDATAOUT ...
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... Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Description (1) (1) (1) (1) (2) (3) (3) (3) (3) Min Typ — 2 — 1.5 — 350 — 350 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 Min Typ Max Units -20 +20 ppm ...
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... Data Sheet VSC8113 DC Characteristics Table 15: PECL and TTL Inputs and Outputs Parameters Description Output HIGH V OH voltage (PECL) Output LOW V OL voltage (PECL) O/P Common V Mode Range OCM (PECL) Differential V Output Voltage OUT75 (PECL) Differential V Output Voltage OUT50 (PECL) Input HIGH V IH ...
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... Industrial Operating Temperature Range ...................................................................... -40 Page 16 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Description DD (1) ) Potential to GND..........................................................................-0.5V to +6V ).......................................................................................... +3.3V or +5. ambient equivalent to 0 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 (Max) Units 480 mA 1.6 W +0.5V DDP + 0. +125 C o ...
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... Data Sheet VSC8113 Package Pin Description Table 17: Pin Definitions Signal Pin FACLOOP 1 VDD 2 CRUEQLP 3 RESET 4 LOOPTIM0 VDDP 9 TXDATAOUT+ 10 TXDATAOUT- 11 VSS 12 TXCLKOUT+ 13 TXCLKOUT- 14 VDDP 15 N/C 16 LOSDETEN_ 17 VSS 18 RXCLKIN+ 19 RXCLKIN- 20 VDDP 21 OOF 22 DSBLCRU 23 RXDATAIN+ 24 RXDATAIN VDD 28 REFCLKP+ 29 REFCLKP- 30 G52154-0, Rev 4 ...
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... Reference clock input, refer to table 12 I TTL Enable loop timing operation; active HIGH +3.3V +3.3V Power Supply GND Analog Ground (CMU) GND Analog Ground (CMU) No connection +3.3V Analog Power Supply (CMU) Analog CMU external capacitor (see Figure 6, and Table 1) VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 Pin Description G52154-0, Rev 4.2 3/19/99 ...
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... Data Sheet VSC8113 Table 17: Pin Definitions Signal Pin CN1 64 CN2 65 CP2 66 VDDA 67 VDDA 68 VDDA 69 VSSA 70 VSSA 71 VSS 72 N CRULOCKDET VSS 75 VDD 76 N/C 77 N CMULOCKDET VDD 81 TXLSCKOUT 82 TXLSCKIN 83 VSS 84 TXIN7 85 TXIN6 86 VSS 87 TXIN5 88 TXIN4 89 N/C 90 TXIN3 91 TXIN2 92 VSS 93 TXIN1 94 TXIN0 95 N/C 96 G52154-0, Rev 4.2 3/19/99 741 Calle Plano, Camarillo, CA 93012 • ...
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... I TTL Selects between CMU’s or CRU’s REFCLK +3.3V +3.3V Power Supply Equipment loopback, loops low speed byte wide transmit I TTL input data to receive output bus VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 Pin Description G52154-0, Rev 4.2 3/19/99 ...
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... Data Sheet VSC8113 Package Information PIN 100 PIN 1 EXPOSED HEATSINK (NOTE 2) 9.0 X 9.0 (N0TE 2) PIN NOTES: (1) Drawings not to scale. (2) Two styles of exposed heat spreaders may be used; square or oval. (3) All units in millimeters unless otherwise noted G52154-0, Rev 4.2 3/19/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 ...
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... ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery The VSC8113 is manufactured in a 100PQFP package which is supplied by two different vendors. The crit- ical dimensions in the drawing represent the superset of dimensions for both packages. The significant differ- ence between the two packages is in the shape and size of the heatspreader which needs to be considered when attaching a heatsink ...
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... VSC8113QB1 155/622Mb/s Mux/Dmux with CMU and CRU in 100 Pin PQFP Extended Temperature ambient (equivalent ambient to 115 C case) VSC8113QB2 155Mb/s-622Mb/s Mux/Dmux with CMU and CRU in 100 Pin PQFP Industrial Temperature, -40 C ambient case Notice This document contains information on products that are in the preproduction phase of development. The information contained in this document is based on test results and initial product characterization ...
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... Since the byte clock (TXLSCKOUT) clocks both the VSC8113 and the UNI devices important to pay close attention to the routing of this signal. The UNI device in general is a CMOS part which can have very wide spreads in timing (1-11ns clock in to parallel data out for the PM5355), which utilizes most of the 12 ...
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... Table 18 contains recommended values for each of the components. TTL Input Structure The TTL inputs of the VSC8113 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tol- erances (see Table 5). The input structure, shown in Figure 14, uses a current limiter to avoid overdriving the input FETs. ...
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... In addition the output pull down resistor should be placed as close to the VSC8113 pin as possible while the AC-coupling capacitor and the biasing resistors should be placed as close as possible to the optics input pin. The same is true on the receive circuit side ...
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... Data Sheet VSC8113 V +3 INPUT R GND REFCLK and TTL Inputs G52154-0, Rev 4.2 3/19/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Figure 14: Input Structures INPUT Current ...
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... ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Page 28 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 G52154-0, Rev 4.2 3/19/99 ...