idt49c460cjb Integrated Device Technology, idt49c460cjb Datasheet - Page 9

• Manufacturer Part Number: idt49c460cjb
• Description: 32-bit Cmos Error Detection And Correction Unit
• Manufacturer: Integrated Device Technology

IDT49C460/A/B/C/D/E
32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
32-BIT DATA WORD CONFIGURATION
Figure 1, provides all the logic needed for single bit error
correction and double bit error detection of a 32-bit data field.
The identification code indicates 7 check bits are required.
The CB
data and 7 check bits. Table 3 describes the operating mode
available.
generation. For example, check bit C
function of the 16 data input bits marked with an X. Check bits
are generated and output in the Generate and Initialization
Mode. Check bits from the respective latch are passed,
unchanged, in the PASSTHRU or Diagnostic Generate Mode.
Check Bits
Check Bits
Generated
Generated
A single IDT49C460 EDC unit, connected as shown in
Figure 3 indicates the 39-bit data format for two bytes of
Table 6 indicates the data bits participating in the check bit
Syndrome bits are generated by an exclusive-OR or the
C
C
C
C
C
C
C
C
C
C
C
C
C
C
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
pin should be HIGH.
Odd (XNOR)
Odd (XNOR)
Odd (XNOR)
Odd (XNOR)
Even (XOR)
Even (XOR)
Even (XOR)
Even (XOR)
Even (XOR)
Even (XOR)
Even (XOR)
Even (XOR)
Even (XOR)
Even (XOR)
Parity
Parity
Table 6. 32–Bit Modified Hamming Code–Check Bit Encode Chart
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13–31
16
X
X
X
X
X
X
X
X
0
0
is the exclusive-OR
Table 5. 32-Bit Diagnostic Latch Coding Format
17
X
X
X
X
X
X
1
18
X
X
X
X
X
X
2
19
X
X
X
X
X
X
3
20
X
X
X
11.6
4
X
X
X
X
X
CB
CB
CB
CB
CB
CB
CB
CB
CODE ID
CODE ID
DIAG MODE
DIAG MODE
CORRECT
DON'T CARE
generated check bits with the read check bits. For example,
S
generated. Table 7 indicates the decoding of the seven
syndrome bits to identify the bit-in-error for a single bit error,
or whether a double or triple bit error was detected. The all
zero case indicates no errors detected.
complement (correct) single bit errors in the data bits. For
double or multiple error detection, the data available as input
to the Data Out Latch is not defined.
As defined in Table 3, several modes will use the diagnostic
check bits to determine syndrome bits or to pass as check bits
to the SC
indicated bit position for the external control signals.
0
1
2
3
4
5
6
7
n
21
DIAGNOSTIC
DIAGNOSTIC
DIAGNOSTIC
DIAGNOSTIC
DIAGNOSTIC
DIAGNOSTIC
DIAGNOSTIC
DIAGNOSTIC
X
X
X
X
X
X
5
In the Correct Mode, the syndrome bits are used to
Table 5 defines the bit definition for the Diagnostic Latch.
is the XOR of check bits C
Participating Data Bits
Participating Data Bits
0
1
22
X
X
X
X
X
X
X
X
6
0
1
0–7
MILITARY AND COMMERCIAL TEMPERATURE RANGES
23
X
X
X
X
X
X
X
X
7
outputs. The Internal Mode substitutes the
24
X
X
X
8
X
X
X
2584 drw 05
25
X
X
X
X
X
X
9
26
10
X
X
X
X
X
X
X
X
n
from those read with those
27
11
X
X
X
X
X
X
28
12
X
X
X
X
X
X
X
X
29
13
X
X
X
X
X
X
X
X
30
14
X
X
X
X
X
X
2584 tbl 07
2584 tbl 06
31
15
9
X
X
X
X
X
X
X
X