max9214eumtd Maxim Integrated Products, Inc., max9214eumtd Datasheet - Page 13

• Manufacturer Part Number: max9214eumtd
• Description: Programmable Dc-balance 21-bit Deserializers
• Manufacturer: Maxim Integrated Products, Inc.

pullup or pulldown resistors are needed. In DC-balanced
mode, at each unused LVDS data input, pull the inverting
input up to V
verting input down to ground using a 10kΩ resistor. Do
not connect a termination resistor. The pullup and pull-
down resistors drive the corresponding outputs low and
prevent switching due to noise.
Driving PWRDWN low puts the outputs in high imped-
ance, stops the PLL, and reduces supply current to
50µA or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs con-
trolled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid con-
tention of the bused outputs.
There is no required timing sequence for the applica-
tion or reapplication of the parallel rate clock (RxCLK
IN) relative to PWRDWN, or to a power-supply ramp for
proper PLL lock. The PLL lock time is set by an internal
counter. The maximum time to lock is 32,800 clock
periods. Power and clock should be stable to meet the
lock time specification. When the PLL is locking, the
outputs are low.
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
V
quency, surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smallest value capacitor closest to the
supply pin.
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer PC
board with separate layers for power, ground, LVDS
inputs, and digital signals is recommended.
CC
, V
CCO
, PLL V
CC
Input Clock and PLL Lock Time
using a 10kΩ resistor, and pull the nonin-
______________________________________________________________________________________
CC
, and LVDS V
Power-Supply Bypassing
Cables and Connectors
CC
Board Layout
pin with high-fre-
PWRDWN
Programmable DC-Balance
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 15. Human Body ESD Test Circuit
Figure 16. ISO 10605 Contact Discharge ESD Test Circuit
The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/
MAX9222 ESD tolerance is rated for IEC 61000-4-2,
Human Body Model and ISO 10605 standards. IEC
61000-4-2 and ISO 10605 specify ESD tolerance for elec-
tronic systems. The IEC 61000-4-2 discharge components
are C
61000-4-2, the LVDS inputs are rated for ±8kV Contact
Discharge and ±15kV Air Discharge. The Human Body
Model discharge components are C
1.5kΩ (Figure 15). For the Human Body Model, all pins
are rated for ±5kV Contact Discharge. The ISO 10605 dis-
charge components are C
(Figure 16). For ISO 10605, the LVDS inputs are rated for
±8kV Contact Discharge and ±25kV Air Discharge.
VOLTAGE
SOURCE
S
VOLTAGE
SOURCE
VOLTAGE
HIGH-
SOURCE
HIGH-
HIGH-
DC
DC
= 150pF and R
DC
21-Bit Deserializers
CHARGE-CURRENT-
CHARGE-CURRENT-
CHARGE-CURRENT-
LIMIT RESISTOR
LIMIT RESISTOR
LIMIT RESISTOR
50Ω TO 100Ω
50Ω TO 100Ω
150pF
1MΩ
330pF
100pF
C
C
C
S
S
S
D
= 330Ω (Figure 14). For IEC
RESISTANCE
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DISCHARGE
RESISTANCE
DISCHARGE
STORAGE
CAPACITOR
S
STORAGE
CAPACITOR
330Ω
1.5kΩ
2kΩ
R
R
= 330pF and R
R
D
D
D
S
ESD Protection
= 100pF and R
DEVICE
UNDER
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
TEST
D
= 2kΩ
D
13
=