max9316aewp-t Maxim Integrated Products, Inc., max9316aewp-t Datasheet - Page 6

• Manufacturer Part Number: max9316aewp-t
• Description: Max9316a 1 5 Differential Lv Pecl/ Lv Ecl/hstl Clock And Data Driver
• Manufacturer: Maxim Integrated Products, Inc.

The MAX9316A is a low-skew, 1-to-5 differential driver
designed for clock or data distribution. A 2-to-1 MUX
selects one of the two clock inputs, CLK, CLK and
SCLK. The CLK and CLK inputs are differential while the
SCLK is single ended. The MUX is switched by the sin-
gle-ended SEL input. A logic low selects the CLK input
and a logic high selects the SCLK input. The SEL logic
threshold is set by the internal voltage reference V
SEL input can be driven by V
ended (LV)PECL/(LV)ECL signal. The selected input is
reproduced at five differential outputs, Q0 to Q4.
1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
6
18, 20
_______________________________________________________________________________________
PIN
10
11
12
13
14
15
16
17
19
1
2
3
4
5
6
7
8
9
NAME
SCLK
CLK
CLK
N.C.
V
SEL
V
V
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
EN
BB
CC
EE
Detailed Description
Noninverting Q0 Output. Typically terminate with 50Ω resistor to (V
Inverting Q0 Output. Typically terminate with 50Ω resistor to (V
Noninverting Q1 Output. Typically terminate with 50Ω resistor to (V
Inverting Q1 Output. Typically terminate with 50Ω resistor to (V
Noninverting Q2 Output. Typically terminate with 50Ω resistor to (V
Inverting Q2 Output. Typically terminate with 50Ω resistor to (V
Noninverting Q3 Output. Typically terminate with 50Ω resistor to (V
Inverting Q3 Output. Typically terminate with 50Ω resistor to (V
Noninverting Q4 Output. Typically terminate with 50Ω resistor to (V
Inverting Q4 Output. Typically terminate with 50Ω resistor to (V
Negative Supply Voltage
Clock Select Input (Single Ended). Drive low to select the CLK, CLK input. Drive high to select the
SCLK input. The SEL threshold is equal to V
V
Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a
reference for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to V
otherwise, leave it unconnected.
Inverting Differential Clock Input. Internal 45kΩ pullup to V
Noninverting Differential Clock Input. Internal 30kΩ pulldown to V
Single-Ended Clock Input. Internal 30kΩ pulldown to V
Not Internally Connected. Solder to PC board for package thermal dissipation.
Positive Supply Voltage. Bypass V
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Output Enable Input. Outputs are synchronously enabled on the falling edge of the clock input
when EN is low. Outputs are synchronously set to low on the falling edge of the clock input when
EN is high. Internal 30kΩ pulldown to V
CC
CC
.
and V
EE
or by a single-
BB
.
CC
The MAX9316A is synchronously enabled and disabled
with outputs in the low state to eliminate shortened
clock pulses. EN is connected to the input of an edge-
triggered D flip-flop. After power-up, drive EN low and
toggle the selected clock input to enable the outputs.
The outputs are enabled on the falling edge of the
selected clock input after EN goes low. The outputs are
disabled to a low state on the falling edge of the select-
ed clock input after EN goes high. The threshold for EN
is equal to V
For interfacing to differential HSTL and (LV)PECL sig-
nals, the V
to V
EE
EE
and 30kΩ pullup to V
BB
FUNCTION
with 0.1µF and 0.01µF ceramic capacitors. Place the
. Internal 30kΩ pulldown to V
CC
BB
EE
.
range is from 3.0 to 5.5V (with V
and 45kΩ pullup to V
CC
and 45kΩ pulldown to V
CC
CC
CC
CC
CC
CC
EE
- 2V).
- 2V).
- 2V).
- 2V).
- 2V).
.
CC
CC
CC
CC
CC
and 45kΩ pullup to V
- 2V).
- 2V).
- 2V).
- 2V).
- 2V).
Synchronous Enable
Pin Description
EE
and 30kΩ pullup to
CC
.
Power Supply
EE
.
CC
.
CC
;
EE