ds0026 National Semiconductor Corporation, ds0026 Datasheet - Page 7

• Manufacturer Part Number: ds0026
• Description: Dual High-speed Mos Driver
• Manufacturer: National Semiconductor Corporation

Application Hints
With a clock transition of 20V the magnitude of the voltage
generated across C
This has been a hypothetical example to emphasize that
with 20V low rise/fall time transitions, parasitic elements can
not be neglected. In this example, 1 pF of parasitic capaci-
FIGURE 5. Clock Coupling
L
is:
(Continued)
DS005853-20
7
tance could cause system malfunction, because a 7404
without a pull up resistor has typically only 0.3V of noise mar-
gin in the “1” state at 25˚C. Of course it is stretching things to
assume that the inductance, L, completely isolates the clock
transient from the 7404. However, it does point out the need
to minimize inductance in input/output as well as clock lines.
The output is current, so it is more meaningful to examine
the current that is coupled through a 1 pF parasitic capaci-
tance. The current would be:
This exceeds the total output current swing so it is obviously
significant.
Clock coupling to inputs and outputs can be minimized by
using multilayer printed circuit boards, as mentioned previ-
ously, physically isolating clock lines and/or running clock
lines at right angles to input/output lines. All of these tech-
niques tend to minimize parasitic coupling capacitance from
the clocks to the signals in question.
In considering clock coupling it is also important to have a
detailed knowledge of the functional characteristics of the
device being used. As an example, for the MM5262, cou-
pling noise from the 2 clock to the address lines is of no par-
ticular consequence. On the other hand the address inputs
will be sensitive to noise coupled from 1 clock.
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