74lvc1g97gm NXP Semiconductors, 74lvc1g97gm Datasheet
74lvc1g97gm
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74lvc1g97gm Summary of contents
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Low-power configurable multiple function gate Rev. 2 — 9 March 2011 1. General description The 74LVC1G97 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, ...
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... Marking Table 2. Marking Type number 74LVC1G97GW 74LVC1G97GV 74LVC1G97GM 74LVC1G97GF 74LVC1G97GN 74LVC1G97GS [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Fig 1. Logic symbol 74LVC1G97 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning 74LVC1G97 GND 001aan190 Fig 2. Pin configuration SOT363 and SOT457 6.2 Pin description Table 3. Pin description Symbol Pin B 1 GND Functional description [1] Table 4. Function table Input ...
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... NXP Semiconductors 7.1 Logic configurations Table 5. Function selection table Logic function 2-input MUX 2-input AND 2-input OR with one input inverted 2-input NAND with one input inverted 2-input AND with one input inverted 2-input NOR with one input inverted 2-input OR Inverter Buffer ...
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... NXP Semiconductors Fig 11. Buffer 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage ...
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... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level output voltage = 100 HIGH-level ...
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... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay see power dissipation capacitance [1] Typical values are measured at nominal V [ the same as t ...
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... NXP Semiconductors Table 10. Measurement points Supply voltage Input 1. 1.95 V 0.5V 2 2.7 V 0.5V 2.7 V 1 3.6 V 1 5.5 V 0.5V Measurement points are given in Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z ...
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... NXP Semiconductors 13. Transfer characteristics Table 12. Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V positive-going see T+ threshold voltage Figure 16 V negative-going see T threshold voltage Figure 16 V hysteresis voltage (V H Figure Figure 16 [1] Typical values are measured ...
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... NXP Semiconductors T− Fig 16. Transfer characteristic Fig 18. Typical 74LVC1G97 transfer characteristic; V 74LVC1G97 Product data sheet mnb154 Fig 17. Definition (mA 3 All information provided in this document is subject to legal disclaimers. Rev. 2 — 9 March 2011 ...
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... NXP Semiconductors 15. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 1.1 0.30 0.25 mm 0.1 0.8 0.20 0.10 OUTLINE VERSION IEC SOT363 Fig 19. Package outline SOT363 (SC-88) 74LVC1G97 Product data sheet scale ...
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... NXP Semiconductors Plastic surface-mounted package (TSOP6); 6 leads y 6 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) UNIT 0.1 1.1 0.40 0.26 mm 0.013 0.9 0.25 0.10 OUTLINE VERSION IEC SOT457 Fig 20. Package outline SOT457 (SC-74) 74LVC1G97 Product data sheet scale ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 22. Package outline SOT891 (XSON6) ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1115 Fig 23. Package outline SOT1115 (XSON6) ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1202 Fig 24. Package outline SOT1202 (XSON6) ...
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... NXP Semiconductors 16. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor TTL Transistor-Transistor Logic HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model DUT Device Under Test 17. Revision history Table 14. Revision history Document ID Release date 74LVC1G97 v.2 20110309 • ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 19. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC1G97 Product data sheet Low-power configurable multiple function gate 18 ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 7.1 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms ...