74lvc1g80gv NXP Semiconductors, 74lvc1g80gv Datasheet
74lvc1g80gv
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74lvc1g80gv Summary of contents
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Single D-type flip-flop; positive-edge trigger Rev. 08 — 29 August 2007 1. General description The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of ...
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... Package Temperature range 74LVC1G80GW +125 C 74LVC1G80GV +125 C 74LVC1G80GM +125 C 74LVC1G80GF +125 C 4. Marking Table 2. Marking codes Type number 74LVC1G80GW 74LVC1G80GV 74LVC1G80GM 74LVC1G80GF 5. Functional diagram mna649 Fig 1. Logic symbol 74LVC1G80_8 Product data sheet Name Description TSSOP5 plastic thin shrink small outline package ...
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... NXP Semiconductors CP D Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74LVC1G80 GND Q 001aab662 Fig 4. Pin configuration SOT353-1 and SOT753 6.2 Pin description Table 3. Pin description Symbol Pin SOT353-1/SOT753 GND n. 74LVC1G80_8 Product data sheet ...
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... NXP Semiconductors 7. Functional description [1] Table 4. Function table Input HIGH voltage level LOW voltage level. = LOW-to-HIGH CP transition don’t care lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition. 8. Limiting values Table 5. ...
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... NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter I supply current CC I additional supply current CC C input capacitance +125 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage ...
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... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation delay see set-up time HIGH or LOW CP; su see hold time D to CP; see ...
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... NXP Semiconductors input frequency in MHz output frequency in MHz output load capacitance in pF supply voltage number of inputs switching sum of outputs 12. Waveforms D input CP input Q output Measurement points are given in ...
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... NXP Semiconductors Table 9. Measurement points Supply voltage 1. 2.7 V 2 3 5.5 V Test data is given in Table 10. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance Z ...
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... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE ...
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... NXP Semiconductors Plastic surface-mounted package; 5 leads DIMENSIONS (mm are the original dimensions UNIT 0.100 0.40 1.1 0.26 mm 0.013 0.25 0.9 0.10 OUTLINE VERSION IEC SOT753 Fig 11. Package outline SOT753 (SC-74A) 74LVC1G80_8 Product data sheet scale ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 13. Package outline SOT891 (XSON6) ...
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... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74LVC1G80_8 20070829 • Modifications: In Section 10 “ ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 14 Abbreviations ...