74lvc169bq NXP Semiconductors, 74lvc169bq Datasheet

74lvc169bq

Manufacturer Part Number

74lvc169bq

Description

Presettable Synchronous 4-bit Up/down Binary Counter

Manufacturer

NXP Semiconductors

Datasheet

1.74LVC169BQ.pdf (22 pages)

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1. General description

The 74LVC169 is a high-performance, low-power, low-voltage, Si-gate CMOS device and

superior to most advanced CMOS compatible TTL families.

The 74LVC169 is a synchronous presettable 4-bit binary counter which features an

internal look-ahead carry circuitry for cascading in high-speed counting applications.

Synchronous operation is provided by having all ﬂip-ﬂops clocked simultaneously so that

the output (pins Q0 to Q3) change coincident with each other when so instructed by the

count-enable (pins CEP and CET) inputs and internal gating. This mode of operation

eliminates the output counting spikes that are normally associated with asynchronous

(ripple clock) counters. A buffered clock (pin CP) input triggers the four ﬂip-ﬂops on the

LOW-to-HIGH transition of the clock. The counter is fully programmable; that is, the

outputs may be preset to any number between 0 and it’s maximum count. Presetting is

synchronous with the clock and takes place regardless of the levels of the count enable

inputs. A LOW level on the parallel enable (pin PE) input disables the counter and causes

the data at the Dn input to be loaded into the counter on the next LOW-to-HIGH transition

of the clock. The direction of the counting is controlled by the up/down (pin U/D) input.

When pin U/D is HIGH, the counter counts up, when LOW, it counts down. The

look-ahead carry circuitry is provided for cascading counters for n-bit synchronous

applications without additional gating. Instrumental in accomplishing this function are two

count-enable (pins CEP and CET) inputs and a terminal count (pin TC) output. Both

count-enable (pins CEP and CET) inputs must be LOW to count. Input pin CET is fed

forward to enable the terminal count (pin TC) output. Pin TC thus enabled will produce a

LOW-level output pulse with a duration approximately equal to a HIGH level portion of

pin Q0 output. The LOW level pin TC pulse is used to enable successive cascaded

stages. The 74LVC169 use edge triggered J-K type ﬂip-ﬂops and have no constraints on

changing the control of data input signals in either state of the clock. The only requirement

is that the various inputs attain the desired state at least a set-up time before the next

LOW-to-HIGH transition of the clock and remain valid for the recommended hold time

thereafter. The parallel load operation takes precedence over the other operations, as

indicated in the mode select table. When pin PE is LOW, the data on the input pins D0 to

D3 enter the ﬂip-ﬂops on the next LOW-to-HIGH transition of the clock. In order for

counting to occur, both pins CEP and CET must be LOW and pin PE must be HIGH. The

pin U/D input determines the direction of the counting. The terminal count output pin TC

output is normally HIGH and goes LOW, provided that pin CET is LOW, when a counter

reaches 15 in the count up mode.The pin TC output state is not a function of the

count-enable parallel (pin CEP) input level. Since pin TC signal is derived by decoding the

ﬂip-ﬂop states, there exists the possibility of decoding spikes on pin TC. For this reason

the use of pin TC as a clock signal is not recommended; see the following logic equations:

count enable = CEP

count up: TC = Q3

count down: TC = Q3

74LVC169

Presettable synchronous 4-bit up/down binary counter

Rev. 04 — 14 October 2004

CET

(U/D)

(U/D).

Product data sheet

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74lvc169bq Summary of contents

Page 1

Presettable synchronous 4-bit up/down binary counter Rev. 04 — 14 October 2004 1. General description The 74LVC169 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC169 is a synchronous ...

Page 2

Philips Semiconductors 2. Features 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1 3.6 V CMOS low power consumption Direct interface with TTL levels Inputs accept voltages up to 5.5 V ...

Page 3

... Table 2: Ordering information Type number Temperature range Package 74LVC169D +125 C 74LVC169DB +125 C 74LVC169PW +125 C 74LVC169BQ +125 C 5. Functional diagram Fig 1. Logic symbol. 9397 750 13818 Product data sheet Presettable synchronous 4-bit up/down binary counter Name Description SO16 plastic small outline package ...

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Philips Semiconductors CEP 7 10 CET U/D Fig 3. Logic diagram. 9397 750 13818 Product data sheet Presettable synchronous 4-bit up/down binary counter ...

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Philips Semiconductors 6. Pinning information 6.1 Pinning U 169 CEP 7 GND 8 001aaa644 Fig 4. Pin conﬁguration SO16 and (T)SSOP16 package. 6.2 Pin description Table 3: Symbol U/D ...

Page 6

Philips Semiconductors 7. Functional description 7.1 Function table Table 4: Operating modes Parallel load (Dn Qn) Count up (increment) Count down (decrement) Hold (do nothing) [ HIGH voltage level steady state HIGH voltage level one setup ...

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Philips Semiconductors U/D CEP and CET Illustrated is the following sequence: - Load (preset) to thirteen. - count up to fourteen, ﬁfteen (maximum), zero, one and two. - Inhibit. ...

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Philips Semiconductors 8. Limiting values Table 5: In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol ...

Page 9

Philips Semiconductors Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current LI I quiescent supply current CC ...

Page 10

Philips Semiconductors 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 2 Symbol Parameter [ +85 C amb ...

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Philips Semiconductors Table 8: Dynamic characteristics GND = 2 Symbol Parameter t skew sk(0) C power dissipation capacitance PD per gate ...

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Philips Semiconductors [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [ used to determine the dynamic power dissipation ( ...

Page 13

Philips Semiconductors Fig 10. The up/down control input (U/D) to output (TC) propagation delays. Fig 11. Set-up and hold times for the input (Dn) and parallel enable input (PE). 9397 750 13818 Product data sheet Presettable synchronous 4-bit up/down binary ...

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Philips Semiconductors Fig 12. Set-up and hold times for count enable inputs (CEP and CET) and control input Table 9: Supply voltage V CC 1.2 V 2 3.6 V Fig 13. Load circuitry for switching times. ...

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Philips Semiconductors 13. Application information CP U U/D CP CEP CET least significant 4-bit counter Fig 14. Synchronous multistage counting scheme. 9397 750 13818 Product data sheet Presettable synchronous 4-bit ...

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Philips Semiconductors 14. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

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Philips Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1.80 mm ...

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Philips Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

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Philips Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area ...

Page 20

Philips Semiconductors 15. Revision history Table 11: Revision history Document ID Release date 74LVC169_4 14102004 • Modiﬁcations: Added DHVQFN16 package • Section • Figure 74LVC169_3 20040512 74LVC169_2 19980520 9397 750 13818 Product data sheet Presettable synchronous 4-bit up/down binary counter ...

Page 21

Philips Semiconductors 16. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualiﬁcation III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

Page 22

Philips Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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