74lvth32244 Fairchild Semiconductor, 74lvth32244 Datasheet
74lvth32244
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74lvth32244 Summary of contents
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... Features Input and output interface capability to systems Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH32244), also available without bushold feature (74LVT32244). Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free bus loading Outputs source/sink 32 mA ...
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Connection Diagram (Top Thru View) Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW –I Inputs –O Outputs 0 31 Pin Assignments for FBGA ...
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... Functional Description The 74LVT32244 and 74LVTH32244 contain thirty-two non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identi- cally, but independent of the other. The control pins can be shorted together to obtain full 32-bit operation. The Logic Diagrams V is associated with Bytes 1 and 2 ...
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Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage I V Output Voltage Input Diode Current Output Diode Current Output Current Supply Current per ...
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DC Electrical Characteristics Symbol Parameter I Power Supply Current CCH CC1 I Power Supply Current CCL CC1 I Power Supply Current CCZ CC1 I Power Supply Current CCZ ...
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Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...