74lvt16501a NXP Semiconductors, 74lvt16501a Datasheet

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74lvt16501a

Manufacturer Part Number
74lvt16501a
Description
3.3v Lvt 18-bit Universal Bus Transceiver 3-state
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
The 74LVT16501A is a high-performance BiCMOS product designed for V
3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock (CPAB and CPBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.
When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level.
If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH
transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the
outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
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74LVT16501A
3.3 V LVT 18-bit universal bus transceiver; 3-state
Rev. 04 — 19 May 2006
18-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA to 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Positive-edge triggered clock inputs
Latch-up protection:
ESD protection:
N
N
N
JESD78: exceeds 500 mA
MIL STD 883, method 3015: exceeds 2000 V
Machine model: exceeds 200 V
Product data sheet
CC
operation at

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74lvt16501a Summary of contents

Page 1

... V LVT 18-bit universal bus transceiver; 3-state Rev. 04 — 19 May 2006 1. General description The 74LVT16501A is a high-performance BiCMOS product designed for V 3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data fl ...

Page 2

... Description SSOP56 plastic shrink small outline package; 56 leads; body width 7.5 mm TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm Rev. 04 — 19 May 2006 74LVT16501A Conditions Min Typ pF ...

Page 3

... B15 A15 23 B16 A16 24 B17 A17 26 001aad339 1 OEAB 55 CPAB 2 LEAB 28 LEBA 30 CPBA 27 OEBA CLK to 17 other channels Rev. 04 — 19 May 2006 74LVT16501A 1 OEAB EN1 55 CPAB 2C3 2 LEAB OEBA EN4 30 5C6 CPBA 28 LEBA ...

Page 4

... Pin Description 1 A-to-B output enable input 2 A-to-B latch enable input 3 data input or output A0 4 ground ( data input or output A1 6 data input or output A2 7 voltage supply 8 data input or output A3 Rev. 04 — 19 May 2006 74LVT16501A 56 GND 55 CPAB GND ...

Page 5

... B9 43 data input or output B8 44 data input or output B7 45 data input or output B6 46 ground ( data input or output B5 48 data input or output B4 49 data input or output B3 Rev. 04 — 19 May 2006 74LVT16501A © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...

Page 6

... A-to-B clock input (active rising edge) 56 ground (0 V) [1] Function table Control OEAB LEAB OEBA LEBA Rev. 04 — 19 May 2006 74LVT16501A Input Internal register CPAB An CPBA ...

Page 7

... HIGH-state input voltage LOW-state input voltage HIGH-state output current LOW-state output current none current duty cycle kHz input transition rise and outputs enabled fall rate ambient temperature free air Rev. 04 — 19 May 2006 74LVT16501A Min Max Unit 0.5 +4.6 V [1] 0.5 +7.0 V [1] 0.5 +7.0 V ...

Page 8

... GND OEAB or OEBA don’t care GND outputs HIGH-state outputs LOW-state outputs disabled Rev. 04 — 19 May 2006 74LVT16501A Min Typ Max - 0.85 1 0.2 2.4 2.55 - 2.0 2 0.07 0.2 - 0.3 0.5 - 0.25 0.4 - 0.3 0.5 - 0.36 0.55 ...

Page 9

... Conditions see Figure 5 see Figure 6 see Figure 7 see Figure 5 see Figure 6 see Figure 7 see Figure 8 see Figure 9 see Figure 8 see Figure 9 see Figure 10 Rev. 04 — 19 May 2006 74LVT16501A Min Typ [ GND. CC 11. Min Typ - - - - - - - ...

Page 10

... Figure 6 see Figure 7 see Figure 6 [1] see Figure 5 see Figure 6 see Figure 7 see Figure 5 see Figure 6 see Figure 7 see Figure 8 see Figure 9 see Figure 8 see Figure 9 see Figure 10 see Figure 10 Rev. 04 — 19 May 2006 74LVT16501A 11. Min Typ 2.4 - 2 1 1.5 - 0.5 1.9 1.0 3.2 1.0 2 ...

Page 11

... C. CC amb V I input output Measurement points are given in Table V and V are typical voltage output drop that occur with the output load Rev. 04 — 19 May 2006 74LVT16501A 11. Min Typ 0.3 0 0.2 0 0.3 0 0.2 0 1.2 0.8 1.2 0.8 1.2 0.8 150 - ...

Page 12

... LEBA) pulse width OEBA V I input OEAB V OH output Measurement points are given in Table V is typical voltage output drop that occur with the output load. OH Rev. 04 — 19 May 2006 74LVT16501A 1/f max PLH 001aad254 9. ...

Page 13

... V Measurement points are given in Table The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points Input Output 1.5 V 1.5 V 1.5 V 1.5 V Rev. 04 — 19 May 2006 74LVT16501A PZL PLZ 001aad346 ...

Page 14

... Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Test data MHz 500 ns 2.5 ns Rev. 04 — 19 May 2006 74LVT16501A EXT DUT ...

Page 15

... 0.3 0.22 18.55 7.6 10.4 0.635 0.2 0.13 18.30 7.4 10.1 REFERENCES JEDEC JEITA MO-118 Rev. 04 — 19 May 2006 74LVT16501A detail 1.0 1.2 1.4 0.25 0.18 0.1 0.6 1.0 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...

Page 16

... Product data sheet 3.3 V LVT 18-bit universal bus transceiver; 3-state 2.5 scale (1) ( 0.28 0.2 0.2 14.1 6.2 0.5 0.17 0.1 0.1 13.9 6.0 REFERENCES JEDEC JEITA MO-153 Rev. 04 — 19 May 2006 74LVT16501A detail 8.3 0.8 0.50 1 0.25 0.08 7.9 0.4 0.35 EUROPEAN PROJECTION © ...

Page 17

... JESD17 with JESD78. 3: corrected clock names. 7: changed I conditions V HOLD CC 8: Product specification Product specification - Rev. 04 — 19 May 2006 74LVT16501A Change notice Supersedes - 74LVT16501A_3 = 3.6 V into 3 74LVT16501A_2 - 74LVT16501A_1 - - © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...

Page 18

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 04 — 19 May 2006 74LVT16501A © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...

Page 19

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. All rights reserved. Date of release: 19 May 2006 Document identifier: 74LVT16501A_4 ...

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