74lv138db NXP Semiconductors, 74lv138db Datasheet

74lv138db

Manufacturer Part Number

74lv138db

Description

3-to-8 Line Decoder/multiplexer; Inverting

Manufacturer

NXP Semiconductors

Datasheet

1.74LV138DB.pdf (17 pages)

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1. General description

2. Features

The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible

with 74HC138 and 74HCT138.

The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted

address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive

active LOW outputs (Y0 to Y7).

There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).

Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.

This multiple enable function allows easy parallel expansion of the device to a 1-of-32

(5 lines to 32 lines) decoder with just four 74LV138 devices and one inverter. The

74LV138 can be used as an eight output demultiplexer by using one of the active LOW

enable inputs as the data input and the remaining enable inputs as strobes. Unused

enable inputs must be permanently tied to their appropriate active HIGH or LOW state.

74LV138

3-to-8 line decoder/demultiplexer; inverting

Rev. 03 — 15 November 2007

Wide operating voltage: 1.0 V to 5.5 V

Optimized for low voltage applications: 1.0 V to 3.6 V

Accepts TTL input levels between V

Typical output ground bounce < 0.8 V at V

Typical HIGH-level output voltage (V

Demultiplexing capability

Multiple input enable for easy expansion

Ideal for memory chip select decoding

Active LOW mutually exclusive outputs

ESD protection:

Multiple package options

Speciﬁed from 40 C to +85 C and from 40 C to +125 C

amb

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

= 25 C

) undershoot: > 2 V at V

= 2.7 V and V

= 3.3 V and T

= 3.6 V

amb

= 25 C

Product data sheet

= 3.3 V and

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