74lvq74 STMicroelectronics, 74lvq74 Datasheet

no-image

74lvq74

Manufacturer Part Number
74lvq74
Description
Dual D-type Flip Flop With Preset And Clear
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVQ74
Quantity:
1 212
Part Number:
74LVQ74
Manufacturer:
ST
0
Part Number:
74lvq74M
Manufacturer:
ST
0
Part Number:
74lvq74MTR
Manufacturer:
ST
0
Part Number:
74lvq74TTR
Manufacturer:
ST
0
DESCRIPTION
The 74LVQ74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
HIGH SPEED:
f
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
LOW NOISE:
V
75 TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
MAX
CC
PLH
OH
OLP
CC
=2 A (MAX.) at T
| = I
(OPR) = 2V to 3.6V (1.2V Data Retention)
= 250 MHz (TYP.) at V
= 0.2 V (TYP.) at V
t
PHL
OL
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
= 12mA (MIN) at V
A
=25°C
CC
CC
= 3.3V
CC
= 3.3V
= 3.0V
2
MOS
Table 1: Order Codes
technology. It is ideal for low power and low noise
3.3V applications.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
SOP
Rev. 5
74LVQ74
74LVQ74MTR
74LVQ74TTR
TSSOP
T & R
1/13

Related parts for 74lvq74

74lvq74 Summary of contents

Page 1

... PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVQ74 is a low voltage CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C Figure 1: Pin Connection And IEC Logic Symbols July 2004 = 3 ...

Page 2

... Figure 2: Input And Output Equivalent Circuit Table 3: Truth Table INPUTS CLR Don’t Care Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/13 Table 2: Pin Description PIN N° ...

Page 3

... -55 to 125 Value = 25°C -40 to 85°C -55 to 125°C A Typ. Max. Min. Max. Min. 2.0 2.0 0.8 0.8 2.99 2.9 2.9 2.48 2.48 2.2 2.2 0.002 0.1 0.1 0 0.36 0.44 0.55 0 -25 -25 74LVQ74 Unit °C °C Unit °C ns/V Unit Max 0.1 0. 3/13 ...

Page 4

... Table 7: Dynamic Switching Characteristics Symbol Parameter V Dynamic Low OLP Voltage Quiet V OLV Output (note Dynamic High IHD Voltage Input (note Dynamic Low ILD Voltage Input (note Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. ...

Page 5

... 500 or equivalent pulse generator (typically OUT Test Condition (V) Min. 3 10MHz 3.3 IN Value = 25°C -40 to 85°C -55 to 125°C A Typ. Max. Min. Max. Min CC(opr 74LVQ74 Unit Max (per circuit 5/13 ...

Page 6

... Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) 6/13 ...

Page 7

... Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle) Figure 7: Waveform - Pulse Width 74LVQ74 7/13 ...

Page 8

... DIM. MIN. A 1.35 A1 0.1 A2 1.10 B 0.33 C 0.19 D 8. 5.8 h 0.25 L 0.4 k 0° ddd 8/13 SO-14 MECHANICAL DATA mm. TYP MAX. 1.75 0.25 1.65 0.51 0.25 8.75 4.0 1.27 6.2 0.50 1.27 8° 0.100 inch MIN. TYP. 0.053 0.004 0.043 0.013 0.007 0.337 0.150 0.050 0.228 0.010 0.016 0° 0016019D MAX. 0.069 0.010 0.065 0.020 0.010 0.344 0.157 ...

Page 9

... PIN 1 IDENTIFICATION 1 mm. TYP MAX. 1.2 0.15 1 1.05 0.30 0.20 5 5.1 6.4 6.6 4.4 4.48 0.65 BSC 8˚ 0.60 0. 74LVQ74 inch MIN. TYP. 0.002 0.004 0.031 0.039 0.007 0.004 0.0089 0.193 0.197 0.244 0.252 0.169 0.173 0.0256 BSC 0˚ 0.018 0.024 0080337D MAX. 0.047 0.006 0.041 0.012 ...

Page 10

... DIM. MIN 12 2.1 Po 3.9 P 7.9 10/13 Tape & Reel SO-14 MECHANICAL DATA mm. TYP MAX. 330 13.2 22.4 6.6 9.2 2.3 4.1 8.1 inch MIN. TYP. 12.992 0.504 0.795 2.362 0.252 0.354 0.082 0.153 0.311 MAX. 0.519 0.882 0.260 0.362 0.090 0.161 0.319 ...

Page 11

... Tape & Reel TSSOP14 MECHANICAL DATA DIM. MIN 12 6.7 Bo 5.3 Ko 1.6 Po 3.9 P 7.9 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 6.9 0.264 5.5 0.209 1.8 0.063 4.1 0.153 8.1 0.311 74LVQ74 inch MIN. TYP. MAX. 12.992 0.519 0.882 0.272 0.217 0.071 0.161 0.319 11/13 ...

Page 12

... Table 10: Revision History Date Revision 29-Jul-2004 5 12/13 Description of Changes Ordering Codes Revision - pag. 1. ...

Page 13

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies www.st.com 74LVQ74 13/13 ...

Related keywords