pcf85134 NXP Semiconductors, pcf85134 Datasheet - Page 14

• Manufacturer Part Number: pcf85134
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF85134_1
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing and frame frequency
7.7 Display register
7.8 Segment outputs
The internal logic and the LCD drive signals of the PCF85134 are timed by the frequency
f
f
The internal oscillator is enabled by connecting pin OSC to pin V
output from pin CLK is the clock signal for any cascaded PCF85134 in the system.
Connecting pin OSC to V
external clock input.
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state, which is not suitable for the liquid crystal.
The timing of the PCF85134 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between all the PCF85134 in the system. The timing also generates the LCD
frame frequency which is derived as an integer division of the clock frequency
(see
frequency applied to pad CLK when an external clock is used.
Table 6.
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs, and one column of the display RAM.
The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data resident in the display register. When less than
60 segment outputs are required the unused segment outputs must be left open-circuit.
Frame frequency
clk
clk(ext)
f
fr
, which equals either the built-in oscillator frequency f
=
Table
. The clock frequency f
---------
f
24
clk
LCD frame frequencies
6). The frame frequency is a fixed division of the internal clock or of the
Rev. 01 — 17 December 2009
DD
enables an external clock source. Pin CLK becomes the
clk
determines the LCD frame frequency (f
Universal LCD driver for low multiplex rates
Nominal frame frequency (Hz)
82
osc
or the external clock frequency
SS
. In this case, the
PCF85134
fr
© NXP B.V. 2009. All rights reserved.
).
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