m41t81s STMicroelectronics, m41t81s Datasheet - Page 13

• Manufacturer Part Number: m41t81s
• Description: Serial Access Real-time Clock With Alarms
• Manufacturer: STMicroelectronics

WRITE mode
Data retention mode
In this mode the master transmitter transmits to the M41T81S slave receiver. Bus protocol is
shown in
(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T81S slave receiver
will send an acknowledge clock to the master transmitter after it has received the slave
address see
data byte.
With valid V
WRITE Cycles. Should the supply voltage decay, the power input will be switched from the
V
At this time the clock registers will be maintained by the attached battery supply. On power-
up, when V
For a further, more detailed review of lifetime calculations, please see Application Note
AN1012.
Figure 10. WRITE mode sequence
CC
pin to the battery when V
Figure 10 on page
CC
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
CC
Figure 7 on page 12
returns to a nominal value, write protection continues for t
applied, the M41T81S can be accessed as described above with READ or
S
ADDRESS
SLAVE
13. Following the START condition and slave address, a logic '0'
CC
falls below the Battery Back-up Switchover Voltage (V
and again after it has received the word address and each
ADDRESS (An)
WORD
DATA n
DATA n+1
DATA n+X
REC
AI00591
.
P
13/31
SO
).