CY2213 Cypress Semiconductor Corp., CY2213 Datasheet - Page 2

• Manufacturer Part Number: CY2213
• Description: Lvpecl Outputs, Output Multiplier Select, OE, I2C
• Manufacturer: Cypress Semiconductor Corp.

Document #: 38-07263 Rev. *E
Pin Description
Frequency Table
CY2213 Two-Wire Serial Interface
Introduction
The CY2213 has a two-wire serial interface designed for data
transfer operations, and is used for programming the P and Q
values for frequency generation. S
controlled by the master device. S
data line. The CY2213 is a slave device and can either read or
write information on the dataline upon request from the master
device.
Figure 1 shows the basic bus connections between master
and slave device. The buses are shared by a number of
devices and are pulled high by a pull-up resistor.
Serial Interface Specifications
Figure 2 shows the basic transmission specification. To begin
and end a transmission, the master device generates a start
signal (S) and a stop signal (P). Start (S) is defined as
switching the S
HIGH. Similarly, stop (P) is defined as switching the S
LOW to HIGH while holding the S
signals, data on S
Data is allowed to change only at LOW period of clock, and
must be stable at the HIGH period of clock. To acknowledge,
drive the S
LOW until the S
VDDX
VSSX
XOUT
XIN
VDD
OE
VSS
SER CLK
SER DATA
VDD
VSS
CLKB
CLK
VSS
VDD
S
0
1
S
Pin Name
x16
x8
M (PLL Multiplier)
data
LOW before the S
clk
data
data
falling edge.
Pin Number
from HIGH to LOW while the S
is synchronous with the clock on the S
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
clk
data
clk
3.3V Power Supply for Crystal Driver
Ground for Crystal Driver
Reference Crystal Feedback
Reference Crystal Input
3.3 V Power Supply (all V
Output Enable, 0 = output disable, 1 = output enable (no internal pull-up)
Ground
Serial Interface Clock
Serial Interface Data
3.3V Power Supply (all V
Ground
LVPECL Output Clock (complement)
LVPECL Output Clock
Ground
3.3V Power Supply (all V
PLL Multiplier Select Input, Pull-up Resistor Internal
clk
HIGH. Between these two
rising edge and hold it
is the serial clock line
is a serial bidirectional
25 MHz
31.25 MHz
15.625 MHz
Example Input Crystal Frequency
data
clk
is at
from
clk
.
DD
DD
DD
pins must be tied directly on board)
pins must be tied directly on board)
pins must be tied directly on board)
Serial Interface Format
Each slave carries an address. The data transfer is initiated by
a start signal (S). Each transfer segment is 1 byte in length.
The slave address and the read/write bit are first sent from the
master device after the start signal. The addressed slave
device must acknowledge (Ack) the master device. Depending
on the Read/Write bit, the master device will either write data
into (logic 0) or read data (logic 1) from the slave device. Each
time a byte of data is successfully transferred, the receiving
device must acknowledge. At the end of the transfer, the
master device will generate a stop signal (P).
Serial Interface Transfer Format
Figure 2 shows the serial interface transfer format used with
the CY2213. Two dummy bytes must be transferred before the
first data byte. The CY2213 has only three bytes of latches to
store information, and the third byte of data is reserved. Extra
data will be ignored.
Pin Description
400 MHz
500 MHz
125 MHz
CLK,CLKB
CY2213
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