cs5520-bp Cirrus Logic, Inc., cs5520-bp Datasheet - Page 34

• Manufacturer Part Number: cs5520-bp
• Description: 16/20-bit Bridge Transducer A/d Converters
• Manufacturer: Cirrus Logic, Inc.

34
posed of one byte for command which is trans-
mitted with its LSB first. The command is
followed by three data bytes which make up the
24-bit word to be written to the selected register
of the A/D converter. The three bytes are trans-
mitted lowest order byte first (bits 7 - 0) with the
LSB of the byte transmitted first.
Figure 3 illustrates the power supply connections
to the evaluation board. Voltages of +5 and -5
analog and +5 digital are required.
Using the Evaluation Board
Prior to using the board to evaluate the CS5516
or CS5520 A/D converter, a good understanding
of the full potential of the converter is necessary.
It is recommended that the CS5516/CS5520 de-
vice data sheet be thoroughly read prior to
attemp ting to u se the ev aluation board.
The CS5516 or CS5520 bridge transducer A/D
converter actually contains two A/D converters.
34
VREF Nonratiometric Offset Register
AIN Nonratiometric Offset Register
AIN Ratiometric Offset Register
Conversion Data Register
AGND
Configuration Register
+5V
-5V
Z1
Z2
DAC Register
Gain Register
Register
+
+
47 F
Table 1. Microcontroller commands via RS-232
47 F
C1
C3
0.1 F
0.1 F
Figure 3. Power Supplies
C4
C2
+5VA
-5VA
One of the converters is used to convert the
VREF voltage input, and the other is used to
convert the AIN signal input. Both converters
utilize an on-chip voltage reference to perform
conversions of their respective inputs. Since
both converters use the same reference they
track one another. The digital processing logic
of the A/D converter depends on the presence of
both signals to properly compute a digital output
word. If the evaluation board is configured for
bridge measurement, and no bridge (load cell or
simulator) is connected to the bridge transducer
terminal block, the converter will output a code
of zero because no reference voltage is present
between the VREF+ and VREF- pins.
The span of the AIN input signal is determined
by a combination of the instrumentation ampli-
fier gain (X25), the programmable gain amplifier
(PGA) gain, the magnitude of the voltage be-
tween the VREF+ and VREF- input pins, and
the calibration words for gain and offset. For ex-
DGND
+5
Z3
50(H)
51(H)
53(H)
52(H)
54(H)
55(H)
56(H)
Read
+
CDB5516/CDB5520
47 F
C5
0.1 F
C6
+5VD
D1(H)
D3(H)
D2(H)
D4(H)
D5(H)
D6(H)
Write
DS74DB4
DS74DB3