adc1212d NXP Semiconductors, adc1212d Datasheet
adc1212d
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adc1212d Summary of contents
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... ADC. The device also includes a programmable full-scale SPI to allow a flexible input voltage range (p- (p-p). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1212D is ideal for use in communications, imaging and medical applications. ...
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... T/H ADC CORE INPUT 12-BIT STAGE PIPELINED INBM ERROR CORRECTION AND DIGITAL PROCESSING All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series SDIO/ODS SCLK/DFS CS SPI INTERFACE OTRA CMOS: DA11 to DA0 OUTPUT or DRIVERS LVDS/DDR: DA10_DA11_P to DA0_DA1_P, DA10_DA11_M to DA0_DA1_M ...
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... I clock input 9 I complementary clock input 10 G analog ground 11 O bottom reference; channel top reference; channel B All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series ADC1212D 40 HVQFN64 ...
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... data output bit 7; channel data output bit 8; channel data output bit 9; channel A All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series …continued © NXP B.V. 2011. All rights reserved ...
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... REFBB 11 12 REFBT 13 VCMB AGND 14 INBM 15 INBP 16 Transparent top view Pin configuration with LVDS DDR digital outputs selected All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series …continued HVQFN64 ...
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... DA8 and DA9 multiplexed, complement 57 O differential output data DA10 and DA11 multiplexed, true O differential output data DA10 and DA11 multiplexed, complement Table 2). All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series [1] © NXP B.V. 2011. All rights reserved ...
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... LVDS DDR mode f = 125 Msps; f clk i CMOS mode; f clk MHz i LVDS DDR mode 125 Msps; f clk i All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series Min 0.4 0.4 0.4 55 40 - Conditions [1] [1] Min Typ 2.85 3.0 1.65 1.8 2 ...
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... ADC1212D065; analog supply only Power-down mode Sleep mode peak-to-peak peak-to-peak LOW-medium level medium-HIGH level high impedance; see All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series Min Typ - 1230 - 1120 - 855 - 780 - ...
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... 1 DDO amb 1 DDA DDO INAP INAM All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series Min Typ - 1.2 - 350 - 3 19 ...
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... ADC1212D125 Unit Typ Max Min Typ Max dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... ADC1212D105 ADC1212D125 Min Typ Max Min Typ Max - - 100 - - 100 - = 40 C to +85 amb ADC1212D105 ADC1212D125 Min Typ Max Min Typ Max 75 - 105 100 - 125 - ...
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... T Tamb = 1 dBFS; unless otherwise specified. ADC1212D105 ADC1212D125 Min Typ Max Min Typ Max - ...
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... DAVP DAVM t clk clk clk LVDS DDR mode timing All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series − 13) (N − 12) (N − 11 clk − 13) (N − 12) (N − 11) ...
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... V, V DDA DDO w(SCLK) h SCLK W0 SDIO R/W W1 SPI timing All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series Conditions Min Typ - data to SCLK HIGH - SCLK HIGH - 5 data to SCLK HIGH - SCLK HIGH ...
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... Fig 8. 001aam616 (dBFS δ (%) = 125 Msps s Fig 10. SNR as a function of duty cycle () All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series 16 R (kΩ 150 250 350 Resistance as a function of frequency ...
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... V (V) I(cm) Fig 14. SNR as a function of common-mode input All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series (1) (2) ( 40 C/typical supply voltages amb = +25 C/typical supply voltages amb = +90 C/typical supply voltages ...
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... NXP Semiconductors 11. Application information 11.1 Device control The ADC1212D can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up and remains in this mode as long as pin CS is held HIGH ...
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... DFS is HIGH, two’s complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1212D supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (V The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) ...
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... Figure 18 would be suitable for a baseband application. ADT1-1WT 100 nF Analog input 100 nF Figure 19 is recommended for high frequency applications. In All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series INAP/ R INBP C INAM/ R INBM 001aan679 R ( 100 nF 25 Ω ...
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... System reference and power management 11.3.1 Internal/external references The ADC1212D has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pin VREF and SENSE (programmable steps between 0 dB and 6 dB via control bits INTREF[2:0] when bit INTREF_EN = logic 1 ...
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... VREF connected to pin SENSE and 24) via 330 pF capacitor to AGND to Figure 24 illustrate how to connect the SENSE and VREF pins to select the All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series BANDGAP REFERENCE EXT_ref ADC CORE VREF pin 330 pF capacitor to AGND ...
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... Fig 24. Internal reference via SPI (p- (p-p) Programmable full-scale Level (dB) 0 1 2 3 4 5 6 reserved All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC ...
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... V (see 11.4 Clock input 11.4.1 Drive modes The ADC1212D can be driven differentially (LVPECL). It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin CLKM (pin CLKP should be connected to ground via a capacitor). ...
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... Package ESD Parasitics CLKP CLKM V = common-mode voltage of the differential input stage cm(clk) All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series Sine clock input 005aaa054 b. Sine clock input (with transformer) CLKP CLKM 005aaa172 Figure 28. The common-mode ...
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... Clock input divider The ADC1212D contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = logic 1; see higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed ...
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... DAn_DAn + 1_P; DBn_DBn + 1_P 100 Ω DAn_DAn + 1_M; DBn_DBn + 1_M + - AGND All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series Table RECEIVER 100 Ω 005aaa112 RECEIVER 100 Ω 005aaa113 Table 32) in order to adjust the output logic © ...
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... DAta Valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1212D. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in recommended to shift ahead the DAV (bits DAVPHASE[2:0] = 0b100; ...
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... NXP Semiconductors 11.5.6 Test patterns For test purposes, the ADC1212D can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see can be defined by the user (TESTPAT_USER[11:4]; see TESTPAT_USER[3:0]; see The selected test pattern is transmitted regardless of the analog input. 11.5.7 Output codes versus input voltage Table 16. ...
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... During circuit initialization it does not matter which output data standard has been selected. At power-up, the device enters Pin control mode. A falling edge on pin CS triggers a transition to SPI control mode. When the ADC1212D enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by ...
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... NXP Semiconductors When the ADC1212D enters SPI control mode, the output data format (two’s complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT[1:0] (see Fig 33. Default mode at start-up: SCLK LOW = offset binary ...
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Register allocation map Table 19. Register allocation map Addr Register name Access (hex) Bit 7 Bit 6 0003 Channel index R/W 0005 Reset and R/W SW_ operating mode RST 0006 Clock R/W - 0008 Internal reference R/W - 0011 ...
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... CLKP R/W differential/single-ended clock input select 0 fully differential 1 single-ended - 0 reserved R/W clock input divide disabled 1 enabled R/W duty cycle stabilizer 0 disabled 1 enabled All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series © NXP B.V. 2011. All rights reserved ...
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... LSB and vice versa) R/W output data format 00 offset binary 01 two’s complement 10 gray code 11 offset binary All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series © NXP B.V. 2011. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series [1] clk [1] clk [1] clk [1] clk [1] clk [1] clk clk © ...
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... DAV CMOS output buffer 00 low 01 medium 10 high 11 very high R/W drive strength for DATA CMOS output buffer 00 low 01 medium 10 high 11 very high All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series © NXP B.V. 2011. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series © NXP B.V. 2011. All rights reserved ...
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... 9.1 7.25 9.1 7.25 9.0 7.10 9.0 7.10 0.5 7.5 7.5 8.9 6.95 8.9 6.95 References JEDEC JEITA - - - - - - All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series detail 0.5 0.4 0.1 0.05 0.05 0.1 0.3 European projection SOT804 sot804-3_po Issue date 09-02-24 10-08-06 © NXP B.V. 2011. All rights reserved. ...
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... Low Voltage Differential Signalling Double Data Rate Low-Voltage Positive Emitter-Coupled Logic Most Significant Bit OuT-of-Range Spurious-Free Dynamic Range Signal-to-Noise Ratio Serial Peripheral Interface Transmitter All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series © NXP B.V. 2011. All rights reserved ...
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... Section 10.4 “Typical characteristics” • Section 13 “Abbreviations” has been added to the data sheet. 20100806 Preliminary data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series Change Supersedes notice - ADC1212D_SER v.1 has been added to the data sheet. - © ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series © NXP B.V. 2011. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 March 2011 ADC1212D series © NXP B.V. 2011. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC1212D series All rights reserved. Date of release: 4 March 2011 Document identifier: ADC1212D_SER ...