adc12062biv National Semiconductor Corporation, adc12062biv Datasheet - Page 9

• Manufacturer Part Number: adc12062biv
• Description: 12-bit, 1 Mhz, 75 Mw A/d Converter With Input Multiplexer And Sample/hold
• Manufacturer: National Semiconductor Corporation

Pin Descriptions
AV
DV
AGND
DGND1
DGND2
DB0 – DB11
V
MUX OUT
ADC IN
S0
IN1
CC
CC
V
IN2
These are the two positive analog supply
inputs They should always be connected
to the same voltage source
brought out separately to allow for sepa-
rate bypass capacitors Each supply pin
should be bypassed to AGND with a
0 1 mF ceramic capacitor in parallel with a
10 mF tantalum capacitor
This is the positive digital supply input It
should always be connected to the same
voltage as the analog supply AV
should be bypassed to DGND2 with a
0 1 mF ceramic capacitor in parallel with a
10 mF tantalum capacitor
These are the power supply ground pins
There are separate analog and digital
ground pins for separate bypassing of the
analog and digital supplies The ground
pins should be connected to a stable
noise-free system ground
ground pins should be returned to the
same potential
ground for the converter DGND1 is the
ground pin for the digital control lines
DGND2 is the ground return for the output
databus See Section 6 0 LAYOUT AND
GROUNDING for more information
These are the TRI-STATE output pins en-
abled by RD CS and OE
These are the analog input pins to the mul-
tiplexer For accurate conversions no in-
put pin (even one that is not selected)
should be driven more than 50 mV below
ground or 50 mV above V
This is the output of the on-board analog
input multiplexer
This is the direct input to the 12-bit sam-
pling A D converter For accurate conver-
sions this pin should not be driven more
than 50 mV below AGND or 50 mV above
AV
This pin selects the analog input that will
be connected to the ADC12062 during the
conversion The input is selected based on
the state of S0 when EOC makes its high-
to-low transition Low selects V
selects V
CC
IN2
AGND is the analog
CC
All of the
IN1
but are
CC
high
It
9
MODE
CS
INT
EOC
RD
OE
S H
PD
V
V
V
V
V
TEST
REF
REF
REF
REF
REF
a
b
a
b
16
(FORCE)
(SENSE)
(FORCE)
(SENSE)
(Figure 1) this output goes low when a
2)
ure 6 ) Data output pins DB0 – DB11 are
This pin should be tied to DV
This is the active low Chip Select control
input When low this pin enables the RD
S H and OE inputs This pin can be tied
low
This is the active low Interrupt output
When using the Interrupt Interface Mode
conversion has been completed and indi-
cates that the conversion result is avail-
able in the output latches This output is
always high when RD is held low (Figure
This is the End-of-Conversion control out-
put This output is low during a conversion
This is the active low Read control input
When RD is low (and CS is low) the INT
output is reset and (if OE is high) data ap-
pears on the data bus This pin can be tied
low
This is the active high Output Enable con-
trol input This pin can be thought of as an
inverted version of the RD input (see Fig-
TRI-STATE when OE is low Data appears
on DB0 – DB11 only when OE is high and
CS and RD are both low This pin can be
tied high
This is the Sample Hold control input The
analog input signal is held and a new con-
version is initiated by the falling edge of
this control input (when CS is low)
This is the Power Down control input This
pin should be held high for normal opera-
tion When this pin is pulled low the device
goes into a low power standby mode
These are the positive and negative volt-
age reference force inputs respectively
See Section 4 REFERENCE INPUTS for
more information
These are the positive and negative volt-
age reference sense pins respectively
See Section 4 REFERENCE INPUTS for
more information
This pin should be bypassed to AGND with
a 0 1 mF ceramic capacitor
This pin should be tied to DV
CC
CC